Synthesis failed on ZedBoard (riscv_ex_stage.sv)

[dah29]

Hi, I have some problems with the synthesis of Pulpissimo to ZedBoard target.

ERROR -> "an enum variable may only be assigned to same enum typed variable or one of its values [pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:445]"

I previously ran ./update-ips and and the ./generate-scripts. I'm running a webpack licensed 2020.2 version under Linux (Ubuntu 18.04). Do you know where is the problem? 

I attach the complete log file "vivado.txt"

Code:

Starting synth_design
Using part: xc7z020clg484-1
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_interleaved_ram/ip/xilinx_interleaved_ram.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_private_ram/ip/xilinx_private_ram.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci

WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci

Top: xilinx_pulpissimo
INFO: [Device 21-403] Loading part xc7z020clg484-1
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_merge with formal parameter declaration list [/home/diego/Documents/tfm/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_merge.sv:31]
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_split with formal parameter declaration list [/home/diego/Documents/tfm/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_split.sv:31]
WARNING: [Synth 8-2507] parameter declaration becomes local in hwpe_stream_split with formal parameter declaration list [/home/diego/Documents/tfm/pulpissimo/ips/hwpe-stream/rtl/hwpe_stream_split.sv:32]
WARNING: [Synth 8-2490] overwriting previous definition of module pulp_clock_mux2 [/home/diego/Documents/tfm/pulpissimo/ips/tech_cells_generic/src/deprecated/pulp_clk_cells_xilinx.sv:53]
WARNING: [Synth 8-2490] overwriting previous definition of module pulp_clock_gating [/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/rtl/pulp_clock_gating_xilinx.sv:11]
ERROR: [Synth 8-1587] an enum variable may only be assigned to same enum typed variable or one of its values [/home/diego/Documents/tfm/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:445]
INFO: [Synth 8-2350] module riscv_ex_stage ignored due to previous errors [/home/diego/Documents/tfm/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv:40]
Failed to read verilog '/home/diego/Documents/tfm/pulpissimo/ips/riscv/rtl/riscv_ex_stage.sv'
2 Infos, 7 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
INFO: [Common 17-206] Exiting Vivado at Tue Mar 23 19:31:02 2021...
Makefile:11: recipe for target 'all' failed
make[1]: *** [all] Error 1
make[1]: Leaving directory '/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard'
Makefile:52: recipe for target 'zedboard' failed
make: *** [zedboard] Error 2

[akurth]

Hi,

Thanks for reporting this.

If this is the line where the error occurs, it could be that the declaration and definition of C_DIV, i.e., 

Code:

localparam C_DIV = FP_DIVSQRT ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED;

misses a type.  The type should be fpnew_pkg::unit_type_t.  Could you try if replacing that line with

Code:

localparam fpnew_pkg::unit_type_t C_DIV = FP_DIVSQRT ? fpnew_pkg::MERGED : fpnew_pkg::DISABLED;

solves the problem?

(According to the SystemVerilog standard, C_DIV in the code above should implicitly get that type, because "A parameter declaration with no type or range specification shall default to the type and range of the final value assigned to the parameter, [...]" (Section 6.20.2 in IEEE 1800-2012).  But that is probably too complex for Vivado to implement.)

[dah29]

Hi, Thank you so much, It seems to be solved! But now, I have another problem:

ERROR -> ERROR: [Synth 8-439] module 'xilinx_slow_clk_mngr' not found [pulpissimo/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv:48]

Code:

INFO: [Synth 8-6157] synthesizing module 'fpga_slow_clk_gen' [/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv:24]
    Parameter CLK_DIV_VALUE bound to: 256 - type: integer
    Parameter COUNTER_WIDTH bound to: 8 - type: integer
ERROR: [Synth 8-439] module 'xilinx_slow_clk_mngr' not found [/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv:48]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_slow_clk_gen' [/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv:24]
ERROR: [Synth 8-6156] failed synthesizing module 'safe_domain' [/home/diego/Documents/tfm/pulpissimo/rtl/pulpissimo/safe_domain.sv:12]
ERROR: [Synth 8-6156] failed synthesizing module 'pulpissimo' [/home/diego/Documents/tfm/pulpissimo/rtl/pulpissimo/pulpissimo.sv:13]
ERROR: [Synth 8-6156] failed synthesizing module 'xilinx_pulpissimo' [/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/rtl/xilinx_pulpissimo.v:23]

Before this error I got these warnings. I guess that it is related to the error.

Code:

Starting synth_design
Using part: xc7z020clg484-1
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_interleaved_ram/ip/xilinx_interleaved_ram.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_private_ram/ip/xilinx_private_ram.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci

WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci

[akurth]

Hi, Thank you so much, It seems to be solved!

Thanks for your feedback!  I created a PR to fix this, so the problem should be resolved in future versions.

But now, I have another problem:

ERROR -> ERROR: [Synth 8-439] module 'xilinx_slow_clk_mngr' not found [pulpissimo/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv:48]

[...]

How did you invoke Vivado?  There are Make targets to build the Xilinx IPs before the main FPGA project.  Have these been run (should be the case if you follow the instructions from the ReadMe)?  If they have run, can you post the log files of the synthesis runs of the IPs?

[dah29]

Hi, I invoked Vivado through the zedboard Makefile ("make zedboard").It seems that the Xillinx IPS are built because I locate pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci but I don't know why the file is not found....


I attach the log files

[akurth]

I could reproduce your problem with Vivado 2020.2, so the problem is not on your side.  I have opened an issue to track this problem.

The problem does not occur in Vivado 2020.1 (and earlier), so until this problem is resolved, please use an earlier version of Vivado if you can.  If you are familiar with Vivado's IP system, especially in 2020.2, please do not hesitate to contribute your knowledge to the resolution of the problem.