Synthesis failed on ZedBoard (riscv_ex_stage.sv)

[dah29]

Hi, Thank you so much, It seems to be solved! But now, I have another problem:

ERROR -> ERROR: [Synth 8-439] module 'xilinx_slow_clk_mngr' not found [pulpissimo/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv:48]

Code:

INFO: [Synth 8-6157] synthesizing module 'fpga_slow_clk_gen' [/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv:24]
    Parameter CLK_DIV_VALUE bound to: 256 - type: integer
    Parameter COUNTER_WIDTH bound to: 8 - type: integer
ERROR: [Synth 8-439] module 'xilinx_slow_clk_mngr' not found [/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv:48]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_slow_clk_gen' [/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv:24]
ERROR: [Synth 8-6156] failed synthesizing module 'safe_domain' [/home/diego/Documents/tfm/pulpissimo/rtl/pulpissimo/safe_domain.sv:12]
ERROR: [Synth 8-6156] failed synthesizing module 'pulpissimo' [/home/diego/Documents/tfm/pulpissimo/rtl/pulpissimo/pulpissimo.sv:13]
ERROR: [Synth 8-6156] failed synthesizing module 'xilinx_pulpissimo' [/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/rtl/xilinx_pulpissimo.v:23]

Before this error I got these warnings. I guess that it is related to the error.

Code:

Starting synth_design
Using part: xc7z020clg484-1
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_interleaved_ram/ip/xilinx_interleaved_ram.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_private_ram/ip/xilinx_private_ram.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci

WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci
/home/diego/Documents/tfm/pulpissimo/fpga/pulpissimo-zedboard/ips/xilinx_slow_clk_mngr/ip/xilinx_slow_clk_mngr.xci