Synthesis failed on ZedBoard (riscv_ex_stage.sv)

[akurth]

Hi, Thank you so much, It seems to be solved!

Thanks for your feedback!  I created a PR to fix this, so the problem should be resolved in future versions.

But now, I have another problem:

ERROR -> ERROR: [Synth 8-439] module 'xilinx_slow_clk_mngr' not found [pulpissimo/fpga/pulpissimo-zedboard/rtl/fpga_slow_clk_gen.sv:48]

[...]

How did you invoke Vivado?  There are Make targets to build the Xilinx IPs before the main FPGA project.  Have these been run (should be the case if you follow the instructions from the ReadMe)?  If they have run, can you post the log files of the synthesis runs of the IPs?