Post Synthesis Simulation in ASIC
   I am trying to synthesize the pulpissimo, I don't find any documentation or specific script  for post-synthesis simulation but I have done the below steps

1) replaced the generic_memory, generic_rom with technology-related cells
2) synthesized soc_domain as top and have obtained synthesis netlist and its sdf file
3) I have replaced the with the synthesis netlist in sim/vcompile/rtl/ <-- all other files are same, not sure which files to keep and which one to remove 
3) I have added the CORE and CLK libs with -L option in sim/tcl_files/run.tcl

The modules gf2_fll , pulp_clock_gating , pulp_clock_mux2 , cluster_clock_gating , cluster_clock_inverter, pulp_clock_inverter are not synthesized, is any one these modules need to be synthesized for post-synthesis simulation?

what libraries should i need to keep in ./sim/tcl_files/config/vsim_ips.tcl ?

It will be great if someone can help me here

The FLL is a clock generator, clock mux, clock gating and clock inverter are cells that are being instantiated from the technology libraries. The idea is to replace these 'behavioral' descriptions with the equivalent cells so that you can get something that works for your technology.

This is needed, as we are not allowed to disclose technology specific cells.

Note that the FLL is not strictly needed. Any clock source can be used. This would also change a bit the logic/bypass around the clocking solution which may have to be revised. Basically if you are designing a simpler/slower system you can also bring in the clock externally without something like PLL or FLL providing an internal solution.
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Hi kgf,
Thanks for your reply. One more question I have is,

Can you tell the steps to build the synthesized netlist?

The synthesized netlist needs to be formed as a lib with the use of tech libraries to be able to run in ModelSim.

I have added the TECH_LIBS in /sim/tcl_files/rtl_vopt.tcl but it throws an error as

Error: ../rtl/tb/ Module 'pulpissimo' is not defined.

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