Bitstream generation of Nexys A7 board.
Hello there!

I've been trying to generate the Bitstream of any board supported by you, but specifically, I want to generate for Nexys A7.

While trying this, I have the following error, after executing "$ make nexys rev=nexysA7-50T":

ERROR: [Vivado 12-172] File or Directory '/<my path>/pulpissimo/fpga/pulpissimo-nexys/ips/xilinx_clk_mngr/ip/xilinx_clk_mngr.xci' does not exist
INFO: [Common 17-206] Exiting Vivado at Sun Apr 25 10:19:29 2021...
make[1]: *** [Makefile:11: all] Error 1
make[1]: se sale del directorio '/<my path>/pulpissimo/fpga/pulpissimo-nexys'
make: *** [Makefile:41: nexys] Error 2

I don't know if any Vivado license is required. I followed the README in GitHub, and after executing ./generate-scripts and ./update-ips, export certain env variables, and so on, there is the same issue. I am able to simulate pulpissimo in RTL simulations but in another computer that has QuestaSim license, and I am trying this bitstream generation in another one(that does not have QuestaSim), don't know if that is the problem. 

I tried other boards and it is the same issue.

Thanks for your answer!

EDIT: I realized that you updated the root GitHub with some changes regarding synthesis using Vivado 2020.2. I could fix the problem mentioned before by git pull command. But now, I got these errors:

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 4 threads
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net i_pulpissimo/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_axi_to_axi_lite/i_axi_to_axi_lite/i_axi_burst_splitter/i_axi_burst_splitter_ar_chan/i_axi_burst_splitter_counters/i_idq/head_tail_q[0][free] has multiple drivers: i_pulpissimo/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_axi_to_axi_lite/i_axi_to_axi_lite/i_axi_burst_splitter/i_axi_burst_splitter_ar_chan/i_axi_burst_splitter_counters/i_idq/gen_data_ffs[0].head_tail_q_reg[0][free]/Q, and i_pulpissimo/soc_domain_i/pulp_soc_i/i_soc_interconnect_wrap/i_axi_to_axi_lite/i_axi_to_axi_lite/i_axi_burst_splitter/i_axi_burst_splitter_ar_chan/i_axi_burst_splitter_counters/i_idq/gen_ht_ffs[0].head_tail_q_reg[0][free]/Q.

INFO: [Project 1-461] DRC finished with 16 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2950.625 ; gain = 64.703 ; free physical = 1185 ; free virtual = 7138
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 2 Warnings, 0 Critical Warnings and 17 Errors encountered.
opt_design failed
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Mon Apr 26 11:39:17 2021...
[Mon Apr 26 11:39:17 2021] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'impl_1'
# open_run impl_1
ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open
INFO: [Common 17-206] Exiting Vivado at Mon Apr 26 11:39:21 2021...
make[1]: *** [Makefile:11: all] Error 1
make[1]: se sale del directorio '/home/edgar/Documentos/proyecto_disenno_/pulpissimo/fpga/pulpissimo-genesys2'
make: *** [Makefile:8: genesys2] Error 2

It seems to be something related to this:

always @ (posedge CLK)
y = y + 1;
always @ (posedge CLK2)
y = y + 3;


Thanks again!
We ran into the same initial problem as you had. The easiest fix was just use Vivado 2020.1
Good luck!

Forum Jump:

Users browsing this thread: 1 Guest(s)