Pulpissimo clock frequency
Hi all,

I am planning to do some work on porting the Pulpissimo platform to several different FPGA boards. One will be Kintex KC705 and another one would Zynq ZC706. Potentially, there might also be a port to some of application specific boards, again, based on Kintex chip. 

I have run an out-of-box run for Zedboard just to get the feeling about the sizes of different iPs. One thing that I've noticed is that the clock frequency is set to 20MHz for the Zedboard and that the Vivado synthesis/implementation does report a fail in timing closure even for such a low clock frequency. 

My actual idea was to port to ZC706 and KC706 and to use a clock frequency of somewhere in the neighborhood of 80MHz-100MHz. 
Is this something that should be achievable? What would be a maximal achievable frequency for FPGA synthesis? 

In addition, have you been doing any synthesis runs for TSMC 40nm LP?



First of all, Mr. Wolf (http://asic.ethz.ch/2017/Mr.Wolf.html) is in TSMC40LP, it is a PULPopen platform which uses an earlier version of the PULPissimo as the main micro-controller to which we attach a cluster of cores. It is very similar to the GAP8 design from Greenwave Technologies.

Practically all our code is designed for ASIC integration and should achieve reasonable clock frequencies when mapped to a modern technology (much actually depends on the SRAM access speed). We do not optimize our designs to run faster on FPGAs, but use FPGAs for emulation of the RTL code that we also use for IC design, this is why we are not looking to have faster FPGA mappings. That being said, there is no reason why any of it should not run 50-100 MHz range on the KC705. With a bit of optimization (better mapping), it should also run faster.

Visit pulp-platform.org and follow us on twitter @pulp_platform

Thanks for the quick reply. I just noticed that the actual speed grade of the Zedboard is -1 which if I'm not mistaken is the worst one. TBH, I was not familiar with the genesys2 board but I found that it has the same chip as KC705 (or at least the same configuration and speed grade). I will do my run for that board and see what happens. 

Thanks for the elaborate response, my run was only an initial one and I did not do any exploration there but wanted to get my expectations right. 

From what I learned regarding the Mr.Wolf chip, frequency was 450MHz which is more than what i'm targeting in my application.

Hello KGF.

I have been doing some synthesis runs for FPGA, in particular, I have been using Genesys2 board for my investigation. At the moment, current maximum frequency that is achievable in the FPGA synthesis is lower than 40MHz. I have noticed that the critical path for the synthesis is actually the read path from the APB peripherals (assume it is failing in pready signal of the APB peripheral). My assumption is that it is failing because there are no registers between the prefetch buffer in the riscy and the APB peripheral, through different stages of the interconnects. I do not know about other paths, these are the ones that I found as failing paths when I ran the synthesis with 40MHz and after analyzing the reports files.

I first tried running 100MHz clk period, but the cycle slack was huge (might be that there were additional paths except the one that I mentioned before).

For my tests, I am using a relatively new version of Vivado, 2019.2.

Based on the previous reply from, I would assume I should be able to close the timing @60-80MHz, maybe even 100MHz for the FPGA. I might be doing something wrong but I am using FPGA build configs which are found on git. The one thing that is changed is actually clock frequency.

My intention right now is to understand if what I am trying to do is possible or not so that I can adjust accordingly. If achieving my target frequency for FPGA is completely of the table, I might settle to having an emulated system running at 30-40Mhz range.
Any suggestions on how to tackle this issue would be appreciated.


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