12-30-2021, 01:44 PM
Hello,
First of all, Mr. Wolf (http://asic.ethz.ch/2017/Mr.Wolf.html) is in TSMC40LP, it is a PULPopen platform which uses an earlier version of the PULPissimo as the main micro-controller to which we attach a cluster of cores. It is very similar to the GAP8 design from Greenwave Technologies.
Practically all our code is designed for ASIC integration and should achieve reasonable clock frequencies when mapped to a modern technology (much actually depends on the SRAM access speed). We do not optimize our designs to run faster on FPGAs, but use FPGAs for emulation of the RTL code that we also use for IC design, this is why we are not looking to have faster FPGA mappings. That being said, there is no reason why any of it should not run 50-100 MHz range on the KC705. With a bit of optimization (better mapping), it should also run faster.
Cheers,
KGF
First of all, Mr. Wolf (http://asic.ethz.ch/2017/Mr.Wolf.html) is in TSMC40LP, it is a PULPopen platform which uses an earlier version of the PULPissimo as the main micro-controller to which we attach a cluster of cores. It is very similar to the GAP8 design from Greenwave Technologies.
Practically all our code is designed for ASIC integration and should achieve reasonable clock frequencies when mapped to a modern technology (much actually depends on the SRAM access speed). We do not optimize our designs to run faster on FPGAs, but use FPGAs for emulation of the RTL code that we also use for IC design, this is why we are not looking to have faster FPGA mappings. That being said, there is no reason why any of it should not run 50-100 MHz range on the KC705. With a bit of optimization (better mapping), it should also run faster.
Cheers,
KGF
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