07-28-2022, 05:26 AM
Hello,
Questasim is a commercial EDA tool from Siemens/Mentor. It comes with an installation tool and plenty of documentation as well as support. If you are in academia, there are academic programs your institution can take advantage of to get access to it. As a company you will have to acquire a license (and pay). Unfortunately if you are an unaffiliated individual there are fewer options.
Technically PULP does not require a specific simulator (i.e. Questasim), but we know our code runs when we use this simulator. Other commercial simulators (VCS, ncsim/xcellium, aldec etc..) should in theory all work.. There are also open source RTL simulators like verilator.
The practical reality is that there are still some SystemVerilog constructs that one or the other simulator does not support (or has difficulties) which can cause issues (verilator for example does not support assertions) with the code as it is written. None of it is a serious problem, given some time the code can be cleaned up (or simplified), newer versions of the tools have better support reducing these issues, at the very worst, simulator specific IFDEFs can be added. BUT, we state that we use Questasim, so that people are aware with which simulator we usually work (we also ended up using both VCS and xcellium in different projects) meaning that we cleaned it up to make sure it will work with Questasim.
We are moving more and more to have code that supports Verilator, but again, the code base is large, and there are could still be some bits and pieces that needs to be cleaned up for Verilator. As this is an open source project, this is also where contributions are needed, we are happy to accept PR for fixes for compatibility issues of simulators.
Hope that helps
KGF
Questasim is a commercial EDA tool from Siemens/Mentor. It comes with an installation tool and plenty of documentation as well as support. If you are in academia, there are academic programs your institution can take advantage of to get access to it. As a company you will have to acquire a license (and pay). Unfortunately if you are an unaffiliated individual there are fewer options.
Technically PULP does not require a specific simulator (i.e. Questasim), but we know our code runs when we use this simulator. Other commercial simulators (VCS, ncsim/xcellium, aldec etc..) should in theory all work.. There are also open source RTL simulators like verilator.
The practical reality is that there are still some SystemVerilog constructs that one or the other simulator does not support (or has difficulties) which can cause issues (verilator for example does not support assertions) with the code as it is written. None of it is a serious problem, given some time the code can be cleaned up (or simplified), newer versions of the tools have better support reducing these issues, at the very worst, simulator specific IFDEFs can be added. BUT, we state that we use Questasim, so that people are aware with which simulator we usually work (we also ended up using both VCS and xcellium in different projects) meaning that we cleaned it up to make sure it will work with Questasim.
We are moving more and more to have code that supports Verilator, but again, the code base is large, and there are could still be some bits and pieces that needs to be cleaned up for Verilator. As this is an open source project, this is also where contributions are needed, we are happy to accept PR for fixes for compatibility issues of simulators.
Hope that helps
KGF
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