Changing Pulpissimo core to cv32e40s

[ivanhira]

Hi, 

I was trying to implement a solution to add AES and maybe other crypto extensions in Pulpissimo. I tried to change the core to a variant of the RI5CY, CV32E40S that support some of that extensions. 
When I run a test that worked on the original core, the JTAG halts the core in the simulation. 

I was wondering if there is something to do with the SDK (by the way, i'm using this platform for a while so i'm still using releases 7.0 and pulp-sdk) or the toolchain to make it work, or is it just a problem in the connection of the core. There are quite a few more ports so, just to start trying, I left some of the ports that seemed optional from the documentation. 

Thanks in advance.

[kgf]

Not sure I understand the issue here. The PULP SDK contains a compiler that supports the extensions. Such a code would not execute on a core that does not have these add-ons. during compilation you can ask vanilla RISC-V code to be generated using compiler flags.

Similarly the addons on CV32E40S (those names from OpenHW..) would not compile with that toolchain.

It is hard to pinpoint where the issue could be.. To the outside the various cores (Ibex, CV32e40... ) should have the same interface.. that should not be the issue. of course there is always some improvements and additions which could have had an unexpected outcome (i.e. OpenHW is not running regression on PULPissimo)..

Questions that come to mind are, what test are you running that worked before and is not working now, how did you compile it (i.e. flags), Is the simulation at RTL, do you see any warnings, errors?

Cheers,
Frank