Synthesizable Version of the HERO Project Accelerator
When trying to run the setup for RTL simulation of the HERO Project's accelerator through synthesis, two modules are not synthesizable, namely axi_sim_mem and apb_stdout. Are there preexisting versions of these two modules that will pass synthesis, or would I just have to try and make them synthesizable while trying to maintain the default functionality as much as possible? TIA
Both of those modules are used for simulation purposes and make life easier when you want to run RTL level simulations. For synthesis (both FPGA and ASIC) they should not be used.

axi_sim_mem is a generic memory that can be initialized for simulation purposes.

/// Infinite (Simulation-Only) Memory with AXI Slave Port
/// The memory array is named `mem`, and it is *not* initialized or reset. This makes it possible to
/// load the memory of this module in simulation with an external `$readmem*` command, e.g.,

Assume you have a 256kB memory, and you have a system that only has a JTAG connection.. it would have taken you about a million simulation cycles to initialize/load this memory, with this simulation model you could initialize it directly at the start of the simulation. These have to be changed to actual memories/ROMs in synthesis.

The second one is also a help, it basically adds a simulation instance to the APB bus, so any printf command you have magically appears on your simulation console (rather than for example going through the UART as a serial bitstream).

Note that in HERO, the controller part is a PULPISSIMO, so you can see more of the documentation there.

HERO (the one with ARM offload to RV32 cores) is not so much in use in actual FPGAs these days (2024), and there were a lot of updates to how we manage configurations (i.e bender). I have asked a colleague to respond with suggested make TARGETs that generate the configuration for the synthesizable versions.
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Hello ajgaspar,
To synthesize the legacy HERO (Arm + Pulp cluster) for the ZCU102 you will need to use different scripts from the simulation one.
The `make all` target in hero/hardware/fpga/Makefile will start the synthesis.

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