Booting Pulpissimo from SPI - post silicon

I have a Pulpissimo chip we sent to a foundry to manufacture. It was synthesized based on pulpissimo releases v7.0.0. We have managed to run a couple of tests on 20MHz.
The problem is when trying to boot from SPI by forcing '00' on bootsel, the spi pads does not respond. We have tried keeping the jtag connector on or disconnecting it from the board. 

Also, on Questasim, when trying to boot from a mode different than the specified from the RTL, e.g., STANDALONE and SPI_FLASH on and forcing '00' on bootsel in the simulation, the transcript posts Branch decision X, when trying to load the 2nd page. The flash content is erased because I did not call the simulation with the arguments to load the program on the flash, but still it should get the error after loading the program and trying to run it, right?

I appreciate if there are any suggestions on how we can make the boot work.

Thanks in advance, Ivan.

Debugging actual implementations is always a bit challenging. There is after all also technology specific components (i.e. the I/O pads, memories) as well as chip level implementation issues (timing, power) involved.

Please understand that we do not really have the time to actually walk through the debug with you, but I could offer a couple of steps to check things
a) do you get life out of the chip otherwise, i.e. can you access it via JTAG? That should allow you to run programs on the core.
b) What exactly do you mean no response from SPI pads, are they at a constant level, floating? Do you have the means to check the signals?

If the chip is otherwise working (i.e. a) , it is easier to work your way from the working parts to the ones that cause issues. SPI connection has two parts, not only your side, but also the Flash side. The timing between the two may not be correct, the PCB might have issues, or even the flash might be defect.

In one of our designs, the error was that we made a mistake in labelling/documenting the pins.. So all pins were there and connected, but RST and CLK signals were swapped (i.e. pin 40 was supposed to be CLK and 41 RST, but in reality it was 41,40).
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