Is there any RTL generator for pulp platform?

i just tried pulp platform and i've done simulation with pulp-sdk and pulp
By the way, i want to develop pulp cores. Is there any RTL generator? i've seen rocket chip with chisel language. 
Is there any same things like chisel in pulp-platform?

Then, if i want to modify some modules at pulp-platform, there's only way to do is modify system verilog code? 

Thanks for reading. Smile

Yes, PULP is developed and maintained as a SystemVerilog based code-base. While this may look daunting for newcomers, it is a more natural environment for hardware developers. Of course this may not be for everyone, and therefore several different projects have been developed (outside of PULP) supporting different approaches including chisel from UC Berkeley. Fell free to explore these if SystemVerilog is not your thing.

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thx! i just started pulpissimo examples.
so, then if i want to using pulp platform, i need to learn systemverilog.

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