Hello there,

I currently collect information for my bachelor thesis and want to compare popular RISC-V implementations.
You have a nice graphic 
[Image: pulp_family4.png]

Does there exist a documentation or has somebody knowledge about how the RISC-V cores match to for example ARM cores.
For example:

RI5CY <-> ARM cortex M0
PULPino <-> ARM cortex M0

Greetings from Munich,


The people over at Si-Five compare their cores here for example https://www.sifive.com/core-designer (scroll to the bottom)
Hey Aaron,

Thanks for the info, SiFive indeed has a nice breakdown, and we should also do something similar. As a research group we do not have the same manpower to work on these things, so it takes a bit of time for us to get it done.  

Generally, the following would hold true:
  • RI5CY is something that would compare to ARM M4(F) in terms of capability. (There is a FPU option in RI5CY)
  • Zero/Micro Riscy is more like the ARM M0/1/3 core
  • Ariane is a 64bit core, more similar to a ARMV8-A architecture, a bit like A53 and A57, but implements a simpler architecture (single issue, in order) 
Notice that RI5CY is the RISC-V core, and PULPino is the (older and simpler) micro-controller that can use RI5CY (or zero-riscy or micro-riscy) as its core. The newer micro-controller architecture is called (PULPissimo) and it can also use any of the three 32bit cores we have.

I hope that helps
Visit pulp-platform.org and follow us on twitter @pulp_platform
Thanks that helps Smile.

I decided to group the implementations in four groups:
- 0: No MMU, No FPU
- 1: No MMU, FPU (F and maybe D extension)
- 2: No MMU but Physical Memory Protection (PMP), FPU
- 3: MMU, FPU, Linux support

Your platform would be classified as:
- Pulp Platform
0: Micro-riscy (very small), Zero-Riscy
1-2: RI5CY (partially support PMP)
3: Ariane

I might add another group for high performance out-of-order architectures.

Thanks again for the info.

Greetings from Munich,


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