ri5cy debugger access to memory and breakpoint facility
#1
Hello again!

The documentation for the ri5cy core, although getting better, is still a little "light" on details for the debugger hardware.

Is there any facility available for accessing memory whilst in debugging mode?
if not, how is it proposed that memory should be accessed when debugging?

what would be the suggested mechanism for implementing a breakpoint mechanism such the executing programme can be run up to a point then the debugger activated?
(I already have a simulation where I can single step the core at a specified simulation clock count, in reality this needs to be at a specified PC).

Thanks in advance
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