Hi Andreas,
After some debugging, I managed to find the problem.
First, in xne_wrap.sv I believe it's supposed to be:
.periph_wen (hwacc_cfg_slave.wen )
And not:
.periph_wen (~hwacc_cfg_slave.wen )
In addition, in cluster_clock_gating.sv, the clock gating is not really implemented and I understand this is because you can't do it on FPGA. However, with the existing code, the functionality in hwpe_ctrl_regfile_latch.sv seems to be broken, since it looks like it relies on clock gating.
The consequence is that when I write some value to a certain register, all the registers get this value.
In order to make it work, I used the code for clock gating from pulpissimo. However, I believe this works only in simulations and not on the FPGA. How do I fix the problem?
Edit:
For now, I fixed it by using the original cluster_clock_gating.sv file (with no clock gating), and changed the condition in the latch_wdata process in hwpe_ctrl_regfile_latch.sv to:
Instead of:
Worked for me in simulation. Haven't tried it on FPGA yet.
Thanks,
Adi
After some debugging, I managed to find the problem.
First, in xne_wrap.sv I believe it's supposed to be:
.periph_wen (hwacc_cfg_slave.wen )
And not:
.periph_wen (~hwacc_cfg_slave.wen )
In addition, in cluster_clock_gating.sv, the clock gating is not really implemented and I understand this is because you can't do it on FPGA. However, with the existing code, the functionality in hwpe_ctrl_regfile_latch.sv seems to be broken, since it looks like it relies on clock gating.
The consequence is that when I write some value to a certain register, all the registers get this value.
In order to make it work, I used the code for clock gating from pulpissimo. However, I believe this works only in simulations and not on the FPGA. How do I fix the problem?
Edit:
For now, I fixed it by using the original cluster_clock_gating.sv file (with no clock gating), and changed the condition in the latch_wdata process in hwpe_ctrl_regfile_latch.sv to:
Code:
if ((ClocksxC[k][l] == 1'b1) && (WAddrOneHotxD[k][l]))
Code:
if( ClocksxC[k][l] == 1'b1)
Thanks,
Adi