What do I need to do before a taping out of PULPino?
I am a student  a complete novice in SOC design. Our tutor wants to implement a RISCV chip design on the extra area of the MPW. If I want to tape out PULPino, what should I verify first?

As far as I know, PULPino is a very mature project, and it has been taped out in different processes, so my current idea is:

1. Perform a Verilog simulation test. The assembly code of the instruction is compiled into a binary file to be read by Verilog's readmemh function, and then all instructions are tested one by one until all instructions pass the test. This part of the test should only involve the operation of the instruction set in the RISCY core.

2. Perform FPGA prototype verification on PULPino SOC. The purpose of this process is to download the SOC's Verilog code to the FPGA and then run the program on the FPGA. It may be necessary to use GDB and OpenOCD for debugging.

Is my idea correct? Does the PULPino project support the above two verifications? Can you give me some advice? And what should be noted in the tool chain, environment, SDK, etc.?


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What do I need to do before a taping out of PULPino? - by zhouqiang - 04-14-2019, 12:35 PM

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