04-15-2019, 06:59 AM
Hello Zhouqiang,
There is nothing really wrong with your general description, and the methods you describe are not wrong. However, there are some other issues you need to look at as well.
There is nothing really wrong with your general description, and the methods you describe are not wrong. However, there are some other issues you need to look at as well.
- RI5CY is the core, and PULPIno is the system that adda memories and peripherals around it.
- Just making a PULPino is usually not very interesting for most people we discuss with. The usual use case, is that people take the core (RI5CY) and build it as part of their own system. They then use PULPino as a development/verification system.
- The description you have in 1) would be needed for such a customized system (Take RI5CY merge with your own custom system). For PULPino, complete testbenches for System Verilog exist. So if you are not changing anything and using it as it is, you can directly go ahead.
- Initializing the memories with readmem is a common way of accelerating simulation, however, if you want to have (later) a chip working, you also have to make sure that you can program the system externally (either through a JTAG interface, external SPI or smtg else).
- There is already an FPGA prototype available for the Zed board. You can directly use it. That particular solution uses a more custom debugging solution, but generally what you want in 2) already exists you can use it directly.
- If you want to make an ASIC with any of the PULP items, there is still some work to be done. We can not release technology specific information (clock generators, I/O cells, memories), so there is a generic library that emulates the behavior of these cells. Once you select a technology (say TSMC65), you need to replace these generic cells with technology specific cells. Especially memories will have a large impact on the overall performance of the system, and you might need to adjust your constraints around what is feasible in the technology.
- We try to keep the code tool chain neutral, I think it should work with any combination of major EDA tools as well as increasing support for open source EDA.
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