Pulpissimo synthesis
#1
Hi,

are you having some scripts or tools to help making correct code parsing for synthesis?
I have made my own list, but don't know which files should be included. For example there is axi_slice_dc_master_wrap.sv under axi and pulp_soc.
Is there some automation hidden for src_files.yml files under IPs and RTL?

Currently when running synthesis with dc_shell, it gives errors from some of IPs. I assume that those are not needed in Pulpino implementation.
Reply
#2
Hi, I cannot try right now but you should be able to generate that by adding something like this to the generate_scripts script in the PULPissimo root (assuming you have a directory called 'synthesis/analyze'):

ipdb.export_synopsys(script_path="synthesis/analyze", source='ips')
ipdb.export_synopsys(script_path="synthesis/analyze", source='rtl')
ipdb.generate_synopsys_list("synthesis/analyze/ips_add_files.tcl", source='ips', analyze_path='scripts/analyze_auto/ips')
ipdb.generate_synopsys_list("synthesis/analyze/rtl_add_files.tcl", source='rtl', analyze_path='scripts/analyze_auto/rtl')
Reply
#3
hello,
Have you done pulpino synthesis?I am doing synthesis for pulpino,and encountered some difficulties,if you have done synthesis for pulpino,can I get some help from you?

(05-07-2019, 05:48 PM)fconti Wrote: Hi, I cannot try right now but you should be able to generate that by adding something like this to the generate_scripts script in the PULPissimo root (assuming you have a directory called 'synthesis/analyze'):

ipdb.export_synopsys(script_path="synthesis/analyze", source='ips')
ipdb.export_synopsys(script_path="synthesis/analyze", source='rtl')
ipdb.generate_synopsys_list("synthesis/analyze/ips_add_files.tcl", source='ips', analyze_path='scripts/analyze_auto/ips')
ipdb.generate_synopsys_list("synthesis/analyze/rtl_add_files.tcl", source='rtl', analyze_path='scripts/analyze_auto/rtl')

What about PULPino?I am trying to synthesize PULPino,Can PULPino do this too?
Reply
#4
Zhouqinang, I have synthesized Pulpino over year ago. Here are files you need to analyze with commands to Synopsys Design Compiler (I can not quarantee that this is situation today)

MikkeN

analyze -library WORK -format sverilog {
   ../pulpino/ips/axi/axi_node/apb_regs_top.sv \
   ../pulpino/ips/axi/axi_node/axi_address_decoder_AR.sv \
   ../pulpino/ips/axi/axi_node/axi_address_decoder_AW.sv \
   ../pulpino/ips/axi/axi_node/axi_address_decoder_BR.sv \
   ../pulpino/ips/axi/axi_node/axi_address_decoder_BW.sv \
   ../pulpino/ips/axi/axi_node/axi_address_decoder_DW.sv \
   ../pulpino/ips/axi/axi_node/axi_AR_allocator.sv \
   ../pulpino/ips/axi/axi_node/axi_ArbitrationTree.sv \
   ../pulpino/ips/axi/axi_node/axi_AW_allocator.sv \
   ../pulpino/ips/axi/axi_node/axi_BR_allocator.sv \
   ../pulpino/ips/axi/axi_node/axi_BW_allocator.sv \
   ../pulpino/ips/axi/axi_node/axi_DW_allocator.sv \
   ../pulpino/ips/axi/axi_node/axi_FanInPrimitive_Req.sv \
   ../pulpino/ips/axi/axi_node/axi_multiplexer.sv \
   ../pulpino/ips/axi/axi_node/axi_node.sv \
   ../pulpino/ips/axi/axi_node/axi_node_wrap.sv \
   ../pulpino/ips/axi/axi_node/axi_node_wrap_with_slices.sv \
   ../pulpino/ips/axi/axi_node/axi_regs_top.sv \
   ../pulpino/ips/axi/axi_node/axi_request_block.sv \
   ../pulpino/ips/axi/axi_node/axi_response_block.sv \
   ../pulpino/ips/axi/axi_node/axi_RR_Flag_Req.sv
}


analyze -library WORK -format sverilog {
   ../pulpino/ips/apb/apb_node/apb_node.sv \
   ../pulpino/ips/apb/apb_node/apb_node_wrap.sv
}

analyze -library WORK -format sverilog {
../pulpino/ips/axi/axi_mem_if_DP/axi_mem_if_MP_Hybrid_multi_bank.sv \
   ../pulpino/ips/axi/axi_mem_if_DP/axi_mem_if_multi_bank.sv \
   ../pulpino/ips/axi/axi_mem_if_DP/axi_mem_if_DP_hybr.sv \
   ../pulpino/ips/axi/axi_mem_if_DP/axi_mem_if_DP.sv \
   ../pulpino/ips/axi/axi_mem_if_DP/axi_mem_if_SP.sv \
   ../pulpino/ips/axi/axi_mem_if_DP/axi_read_only_ctrl.sv \
   ../pulpino/ips/axi/axi_mem_if_DP/axi_write_only_ctrl.sv    
}

analyze -library WORK -format sverilog {
 ../pulpino/ips/axi/axi_spi_slave/axi_spi_slave.sv \
   ../pulpino/ips/axi/axi_spi_slave/spi_slave_axi_plug.sv \
   ../pulpino/ips/axi/axi_spi_slave/spi_slave_cmd_parser.sv \
   ../pulpino/ips/axi/axi_spi_slave/spi_slave_controller.sv \
   ../pulpino/ips/axi/axi_spi_slave/spi_slave_dc_fifo.sv \
   ../pulpino/ips/axi/axi_spi_slave/spi_slave_regs.sv \
   ../pulpino/ips/axi/axi_spi_slave/spi_slave_rx.sv \
   ../pulpino/ips/axi/axi_spi_slave/spi_slave_syncro.sv \
   ../pulpino/ips/axi/axi_spi_slave/spi_slave_tx.sv  
}

analyze -library WORK -format sverilog {
../pulpino/ips/axi/axi_spi_master/axi_spi_master.sv \
   ../pulpino/ips/axi/axi_spi_master/spi_master_axi_if.sv \
   ../pulpino/ips/axi/axi_spi_master/spi_master_clkgen.sv \
   ../pulpino/ips/axi/axi_spi_master/spi_master_controller.sv \
   ../pulpino/ips/axi/axi_spi_master/spi_master_fifo.sv \
   ../pulpino/ips/axi/axi_spi_master/spi_master_rx.sv \
   ../pulpino/ips/axi/axi_spi_master/spi_master_tx.sv  
}

analyze -library WORK -format sverilog {
   ../pulpino/ips/apb/apb_uart_sv/apb_uart_sv.sv \
   ../pulpino/ips/apb/apb_uart_sv/uart_rx.sv \
   ../pulpino/ips/apb/apb_uart_sv/uart_tx.sv \
   ../pulpino/ips/apb/apb_uart_sv/io_generic_fifo.sv \
   ../pulpino/ips/apb/apb_uart_sv/uart_interrupt.sv
}

analyze -library WORK -format sverilog {
   ../pulpino/ips/apb/apb_gpio/apb_gpio.sv
}

analyze -library WORK -format sverilog {
   ../pulpino/ips/apb/apb_event_unit/apb_event_unit.sv \
   ../pulpino/ips/apb/apb_event_unit/generic_service_unit.sv \
   ../pulpino/ips/apb/apb_event_unit/sleep_unit.sv
}

analyze -library WORK -format sverilog {
../pulpino/ips/apb/apb_spi_master/apb_spi_master.sv \
   ../pulpino/ips/apb/apb_spi_master/spi_master_apb_if.sv \
   ../pulpino/ips/apb/apb_spi_master/spi_master_clkgen.sv \
   ../pulpino/ips/apb/apb_spi_master/spi_master_controller.sv \
   ../pulpino/ips/apb/apb_spi_master/spi_master_fifo.sv \
   ../pulpino/ips/apb/apb_spi_master/spi_master_rx.sv \
   ../pulpino/ips/apb/apb_spi_master/spi_master_tx.sv  
}

analyze -library WORK -format sverilog {
../pulpino/ips/apb/apb_pulpino/apb_pulpino.sv    
}

analyze -library WORK -format sverilog {
../pulpino/ips/apb/apb_fll_if/apb_fll_if.sv  
}

analyze -library WORK -format sverilog {
 ../pulpino/ips/axi/core2axi/core2axi.sv  
}

analyze -library WORK -format sverilog {
 ../pulpino/ips/apb/apb_timer/apb_timer.sv \
   ../pulpino/ips/apb/apb_timer/timer.sv  
}

analyze -library WORK -format sverilog {
  ../pulpino/ips/axi/axi2apb/AXI_2_APB.sv \
   ../pulpino/ips/axi/axi2apb/AXI_2_APB_32.sv \
   ../pulpino/ips/axi/axi2apb/axi2apb.sv \
   ../pulpino/ips/axi/axi2apb/axi2apb32.sv
}

analyze -library WORK -format sverilog {
../pulpino/ips/apb/apb_i2c/apb_i2c.sv \
   ../pulpino/ips/apb/apb_i2c/i2c_master_bit_ctrl.sv \
   ../pulpino/ips/apb/apb_i2c/i2c_master_byte_ctrl.sv \
   ../pulpino/ips/apb/apb_i2c/i2c_master_defines.sv    
}

analyze -library WORK -format sverilog {
 ../pulpino/ips/axi/axi_slice_dc/axi_slice_dc_master.sv \
   ../pulpino/ips/axi/axi_slice_dc/axi_slice_dc_slave.sv \
   ../pulpino/ips/axi/axi_slice_dc/dc_data_buffer.v \
   ../pulpino/ips/axi/axi_slice_dc/dc_full_detector.v \
   ../pulpino/ips/axi/axi_slice_dc/dc_synchronizer.v \
   ../pulpino/ips/axi/axi_slice_dc/dc_token_ring_fifo_din.v \
   ../pulpino/ips/axi/axi_slice_dc/dc_token_ring_fifo_dout.v \
   ../pulpino/ips/axi/axi_slice_dc/dc_token_ring.v  
}

analyze -library WORK -format sverilog {
../pulpino/ips/riscv/include/apu_core_package.sv \
   ../pulpino/ips/riscv/include/riscv_defines.sv \
   ../pulpino/ips/riscv/include/riscv_tracer_defines.sv \
   ../pulpino/ips/riscv/riscv_alu.sv \
   ../pulpino/ips/riscv/riscv_alu_basic.sv \
   ../pulpino/ips/riscv/riscv_alu_div.sv \
   ../pulpino/ips/riscv/riscv_compressed_decoder.sv \
   ../pulpino/ips/riscv/riscv_controller.sv \
   ../pulpino/ips/riscv/riscv_cs_registers.sv \
   ../pulpino/ips/riscv/riscv_debug_unit.sv \
   ../pulpino/ips/riscv/riscv_decoder.sv \
   ../pulpino/ips/riscv/riscv_int_controller.sv \
   ../pulpino/ips/riscv/riscv_ex_stage.sv \
   ../pulpino/ips/riscv/riscv_hwloop_controller.sv \
   ../pulpino/ips/riscv/riscv_hwloop_regs.sv \
   ../pulpino/ips/riscv/riscv_id_stage.sv \
   ../pulpino/ips/riscv/riscv_if_stage.sv \
   ../pulpino/ips/riscv/riscv_load_store_unit.sv \
   ../pulpino/ips/riscv/riscv_mult.sv \
   ../pulpino/ips/riscv/riscv_prefetch_buffer.sv \
   ../pulpino/ips/riscv/riscv_prefetch_L0_buffer.sv \
   ../pulpino/ips/riscv/riscv_core.sv \
   ../pulpino/ips/riscv/riscv_apu_disp.sv \
   ../pulpino/ips/riscv/riscv_fetch_fifo.sv \
   ../pulpino/ips/riscv/riscv_L0_buffer.sv  
}

analyze -library WORK -format sverilog {
../pulpino/ips/riscv/riscv_register_file.sv  
}

analyze -library WORK -format vhdl {
../pulpino/ips/apb/apb_uart/apb_uart.vhd \
   ../pulpino/ips/apb/apb_uart/slib_clock_div.vhd \
   ../pulpino/ips/apb/apb_uart/slib_counter.vhd \
   ../pulpino/ips/apb/apb_uart/slib_edge_detect.vhd \
   ../pulpino/ips/apb/apb_uart/slib_fifo.vhd \
   ../pulpino/ips/apb/apb_uart/slib_input_filter.vhd \
   ../pulpino/ips/apb/apb_uart/slib_input_sync.vhd \
   ../pulpino/ips/apb/apb_uart/slib_mv_filter.vhd \
   ../pulpino/ips/apb/apb_uart/uart_baudgen.vhd \
   ../pulpino/ips/apb/apb_uart/uart_interrupt.vhd \
   ../pulpino/ips/apb/apb_uart/uart_receiver.vhd \
   ../pulpino/ips/apb/apb_uart/uart_transmitter.vhd  
}

analyze -library WORK -format sverilog {
 ../pulpino/ips/axi/axi_slice/axi_ar_buffer.sv \
   ../pulpino/ips/axi/axi_slice/axi_aw_buffer.sv \
   ../pulpino/ips/axi/axi_slice/axi_b_buffer.sv \
   ../pulpino/ips/axi/axi_slice/axi_buffer.sv \
   ../pulpino/ips/axi/axi_slice/axi_r_buffer.sv \
   ../pulpino/ips/axi/axi_slice/axi_slice.sv \
   ../pulpino/ips/axi/axi_slice/axi_w_buffer.sv  
}

analyze -library WORK -format sverilog {
 ../pulpino/ips/adv_dbg_if/rtl/adbg_axi_biu.sv \
   ../pulpino/ips/adv_dbg_if/rtl/adbg_axi_module.sv \
   ../pulpino/ips/adv_dbg_if/rtl/adbg_lint_biu.sv \
   ../pulpino/ips/adv_dbg_if/rtl/adbg_lint_module.sv \
   ../pulpino/ips/adv_dbg_if/rtl/adbg_crc32.v \
   ../pulpino/ips/adv_dbg_if/rtl/adbg_or1k_biu.sv \
   ../pulpino/ips/adv_dbg_if/rtl/adbg_or1k_module.sv \
   ../pulpino/ips/adv_dbg_if/rtl/adbg_or1k_status_reg.sv \
   ../pulpino/ips/adv_dbg_if/rtl/adbg_top.sv \
   ../pulpino/ips/adv_dbg_if/rtl/bytefifo.v \
   ../pulpino/ips/adv_dbg_if/rtl/syncflop.v \
   ../pulpino/ips/adv_dbg_if/rtl/syncreg.v \
   ../pulpino/ips/adv_dbg_if/rtl/adbg_tap_top.v \
   ../pulpino/ips/adv_dbg_if/rtl/adv_dbg_if.sv \
   ../pulpino/ips/adv_dbg_if/rtl/adbg_axionly_top.sv \
   ../pulpino/ips/adv_dbg_if/rtl/adbg_lintonly_top.sv  
}

analyze -library WORK -format sverilog {
   ../pulpino/ips/apb/apb2per/apb2per.sv
}

analyze -library WORK -format sverilog {
../pulpino/rtl/components/pulp_clock_gating.sv \
  ../pulpino/rtl/components/cluster_clock_gating.sv \
  ../pulpino/rtl/components/cluster_clock_inverter.sv \
  ../pulpino/rtl/components/cluster_clock_mux2.sv \
  ../pulpino/rtl/components/rstgen.sv \
  ../pulpino/rtl/components/pulp_clock_inverter.sv \
  ../pulpino/rtl/components/pulp_clock_mux2.sv \
  ../pulpino/rtl/components/generic_fifo.sv \
  ../pulpino/rtl/components/sp_ram.sv
}

analyze -library WORK -format sverilog {
  ../pulpino/rtl/axi2apb_wrap.sv \
  ../pulpino/rtl/periph_bus_wrap.sv \
  ../pulpino/rtl/core2axi_wrap.sv \
  ../pulpino/rtl/axi_node_intf_wrap.sv \
  ../pulpino/rtl/axi_spi_slave_wrap.sv \
  ../pulpino/rtl/axi_slice_wrap.sv \
  ../pulpino/rtl/axi_mem_if_SP_wrap.sv \
  ../pulpino/rtl/core_region.sv \
  ../pulpino/rtl/instr_ram_wrap.sv \
  ../pulpino/rtl/sp_ram_wrap.sv \
  ../pulpino/rtl/boot_code.sv \
  ../pulpino/rtl/boot_rom_wrap.sv \
  ../pulpino/rtl/peripherals.sv \
  ../pulpino/rtl/ram_mux.sv \
  ../pulpino/rtl/pulpino_top.sv \
  ../pulpino/rtl/clk_rst_gen.sv \
  ../pulpino/fpga/rtl/pulpino_wrap.v
}
Reply
#5
Hello MikkeN,
Thank you so much for your generous help! Have you tried generating SRAM and boot_rom? Then after the DC is completed, have you simulated it with the generated netlist? How should the simulation after this be done?
Reply
#6
(05-07-2019, 04:19 PM)MikkeN Wrote: Hi,

are you having some scripts or tools to help making correct code parsing for synthesis?
I have made my own list, but don't know which files should be included. For example there is axi_slice_dc_master_wrap.sv under axi and pulp_soc.
Is there some automation hidden for src_files.yml files under IPs and RTL?

Currently when running synthesis with dc_shell, it gives errors from some of IPs. I assume that those are not needed in Pulpino implementation.

Hello Mikken,
     Sorry to bother you again. Now I am trying to write sdc file for synthesizing the PULPino, but the clock for PULPino seems to be a liitle complex, from the vivado .xdc file, it seems that there are three asynchronous clocks, so my question is how should I write sdc file for the PULPino? If you have wrote sdc file, can you share it with me?
Reply


Forum Jump: