Pulpissimo L2 memory access via JTAG
#1
Hello,

I am trying to write and read L2 memory via JTAG . According to datasheet memory map it should be in 0x1c000000...0x1c080000. and in soc_bus_defines there is definition
// MASTER PORT TO L2
`define SOC_L2_START_ADDR        32'h1C00_0000
`define SOC_L2_END_ADDR          32'h1FFF_FFFF


However the above parameters are not used anywhere and I can not succesfully write and read to that area. I get always zeros from  any memory address that i have tried.
So where is the memory located actually ? 
I went through the related RTL codes and found local parameter TCDM_START_ADDRESS, which is set to diffrent memory area, and it looked that might be the used area but still the memory access is not working.

As background:
I have succesfylly read and written quite a many peripheral resister, SOC control registers etc, so the JTAG link as such works.
I have implemented Pulpissomo on KIntex FPGA on Genesys board. The xilinx memories seem to be in shape.

Regards, skor
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#2
I think the code has overtaken the documentation there. We use PULPissimo sometimes as a standalone single core micro-controller, but it is also used as an additional controller (mostly we call it fabric controller) outside our multi-core cluster based systems. The way we access memories (both within the cluster and in PULPissimo) uses the tightly coupled data memory (TCDM) concept which connects a multi-banked memory to a set of cores/accelerators through a connection/arbitration matrix (called Logarithmic interconnect).

When used as a controller with a cluster of cores attached, we call the part, that is outside the cluster the "SOC", and the memory in this SOC (relative to the cores in the cluster) we call L2.

When used standalone, we sometimes just use the name "TCDM" to refer to the same memory structure, and I am afraid this might cause a bit of confusion.

There are also references to SCM (Standard Cell based Memory), which is an (optional) additional part of the memory mapped to latch/FF arrays and are therefore operational at lower voltages than regular memory cuts we have access to.

As for simulation, we suggest to use the SDK for that. The linker defines that moves your core/data to the correct address are already correctly configured for the versions that you check out, handling the lower level details for you.

We are working towards better documentation that should also help with lower level access, but these take time. We are always happy to receive contributions to documentations and clarifications. Simply start a pull request on the GitHub
Visit pulp-platform.org and follow us on twitter @pulp_platform
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#3
(05-08-2019, 07:41 AM)skor Wrote: Hello,

I am trying to write and read L2 memory via JTAG . According to datasheet memory map it should be in 0x1c000000...0x1c080000. and in soc_bus_defines there is definition
// MASTER PORT TO L2
`define SOC_L2_START_ADDR        32'h1C00_0000
`define SOC_L2_END_ADDR          32'h1FFF_FFFF


However the above parameters are not used anywhere and I can not succesfully write and read to that area. I get always zeros from  any memory address that i have tried.
So where is the memory located actually ? 
I went through the related RTL codes and found local parameter TCDM_START_ADDRESS, which is set to diffrent memory area, and it looked that might be the used area but still the memory access is not working.

As background:
I have succesfylly read and written quite a many peripheral resister, SOC control registers etc, so the JTAG link as such works.
I have implemented Pulpissomo on KIntex FPGA on Genesys board. The xilinx memories seem to be in shape.

Regards, skor

Hello skor,


to read/write L2 memory with the JTAG please refer to these memory ranges between line 260 and 264

https://github.com/pulp-platform/pulp_so...ct.sv#L260

As far as I can tell, you should be able to R/W from 1c00_0000 so it is strange that you see all 0s.

The L2 memory is organized as 3 banks, of which one is interleaved.

The 3 banks have the following ranges:

Bank0: [1C00_0000, 1C00_8000)
Bank1: [1C00_8000, 1C01_0000)
Bank Interleaved: [1C01_0000, 1C08_2000)

you may want to try to read and write to the same bank to see whether it works. I can tell that in all our implementations on Silicon this has always worked so far Smile

Best
Davide
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#4
(05-08-2019, 03:44 PM)pschiavo Wrote:
(05-08-2019, 07:41 AM)skor Wrote: Hello,

I am trying to write and read L2 memory via JTAG . According to datasheet memory map it should be in 0x1c000000...0x1c080000. and in soc_bus_defines there is definition
// MASTER PORT TO L2
`define SOC_L2_START_ADDR        32'h1C00_0000
`define SOC_L2_END_ADDR          32'h1FFF_FFFF


However the above parameters are not used anywhere and I can not succesfully write and read to that area. I get always zeros from  any memory address that i have tried.
So where is the memory located actually ? 
I went through the related RTL codes and found local parameter TCDM_START_ADDRESS, which is set to diffrent memory area, and it looked that might be the used area but still the memory access is not working.

As background:
I have succesfylly read and written quite a many peripheral resister, SOC control registers etc, so the JTAG link as such works.
I have implemented Pulpissomo on KIntex FPGA on Genesys board. The xilinx memories seem to be in shape.

Regards, skor

Hello skor,


to read/write L2 memory with the JTAG please refer to these memory ranges between line 260 and 264

https://github.com/pulp-platform/pulp_so...ct.sv#L260

As far as I can tell, you should be able to R/W from 1c00_0000 so it is strange that you see all 0s.

The L2 memory is organized as 3 banks, of which one is interleaved.

The 3 banks have the following ranges:

Bank0: [1C00_0000, 1C00_8000)
Bank1: [1C00_8000, 1C01_0000)
Bank Interleaved: [1C01_0000, 1C08_2000)

you may want to try to read and write to the same bank to see whether it works. I can tell that in all our implementations on Silicon this has always worked so far Smile

Best
Davide

Hello,

I have now started to do RTL simulations with QUESTAsim  , for being able to look inside Pulpissimo. I am running the tb_pulp.sv test which according to simulation transcript is filling L2 memory (message 'loading L2 with JTAG interface') . I have waved all signals in L2 interface, but see no changes in address . Address L2_a_o is actually in 0x7000 all the time for all 4 banks ( there are 4 banks , not 3 as you told in your reply, which is again a bit confusing)  , but I am aware of the offset L2_OFFSET_PRI set thre in line 661 of soc_interconnect.sv

I took DBG_RX_add_i  bus to waves also in simulator ( soc_interconnect.sv). there seems to be the address chanings according to what is happening in test bench. 

Is the some parameter or definition somewhere which I should change to get the accesses going to L2 instead of somewhere else ( where?) . Do I have a wrong configuraion for the whole design and how should i modify it?

Regards , skor
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#5
Hello,

I was finally able to run hello test in questasim and the memory read/write operations were succesfull there ( also checked  waveforms what happened in the memeory interface)  However , my original problem is not yet solved. I have Pulpissimo in FPGA ( Genesys board actually). I am able to access a few register via jtag, but still not yet L2 memory. I looked the hello test testbenhc in detail and it looks that perhaps some configurations to pulpissimo should be done before being able to access memory via jtag.  there is at least jtag_conf_reg ( address 0x1A104074) which is set to value 0x000030 in tb_pulp.sv.  I tried that but it did not help. Is that correct value and is there some settings to be done? 

regards, skor
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#6
(06-06-2019, 06:26 AM)skor Wrote: Hello,

I was finally able to run hello test in questasim and the memory read/write operations were succesfull there ( also checked  waveforms what happened in the memeory interface)  However , my original problem is not yet solved. I have Pulpissimo in FPGA ( Genesys board actually). I am able to access a few register via jtag, but still not yet L2 memory. I looked the hello test testbenhc in detail and it looks that perhaps some configurations to pulpissimo should be done before being able to access memory via jtag.  there is at least jtag_conf_reg ( address 0x1A104074) which is set to value 0x000030 in tb_pulp.sv.  I tried that but it did not help. Is that correct value and is there some settings to be done? 

regards, skor


Were you able to solve this issue ? I am trying to do the same here.
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#7
(09-18-2019, 07:18 AM)AhmedZaky Wrote:
(06-06-2019, 06:26 AM)skor Wrote: Hello,

I was finally able to run hello test in questasim and the memory read/write operations were succesfull there ( also checked  waveforms what happened in the memeory interface)  However , my original problem is not yet solved. I have Pulpissimo in FPGA ( Genesys board actually). I am able to access a few register via jtag, but still not yet L2 memory. I looked the hello test testbenhc in detail and it looks that perhaps some configurations to pulpissimo should be done before being able to access memory via jtag.  there is at least jtag_conf_reg ( address 0x1A104074) which is set to value 0x000030 in tb_pulp.sv.  I tried that but it did not help. Is that correct value and is there some settings to be done? 

regards, skor


Were you able to solve this issue ? I am trying to do the same here.
Hi AhmedZaky,

Could you please elaborate, why and how you try to access the L2 memory externally? I just tried it myself on the Genesys2 board and L2 memory access via GDB (e.g. x/s 0x1c000368)-OpenOCD-JTAG works fine.

Greetings,
Manuel
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