05-08-2019, 08:45 AM
I think the code has overtaken the documentation there. We use PULPissimo sometimes as a standalone single core micro-controller, but it is also used as an additional controller (mostly we call it fabric controller) outside our multi-core cluster based systems. The way we access memories (both within the cluster and in PULPissimo) uses the tightly coupled data memory (TCDM) concept which connects a multi-banked memory to a set of cores/accelerators through a connection/arbitration matrix (called Logarithmic interconnect).
When used as a controller with a cluster of cores attached, we call the part, that is outside the cluster the "SOC", and the memory in this SOC (relative to the cores in the cluster) we call L2.
When used standalone, we sometimes just use the name "TCDM" to refer to the same memory structure, and I am afraid this might cause a bit of confusion.
There are also references to SCM (Standard Cell based Memory), which is an (optional) additional part of the memory mapped to latch/FF arrays and are therefore operational at lower voltages than regular memory cuts we have access to.
As for simulation, we suggest to use the SDK for that. The linker defines that moves your core/data to the correct address are already correctly configured for the versions that you check out, handling the lower level details for you.
We are working towards better documentation that should also help with lower level access, but these take time. We are always happy to receive contributions to documentations and clarifications. Simply start a pull request on the GitHub
When used as a controller with a cluster of cores attached, we call the part, that is outside the cluster the "SOC", and the memory in this SOC (relative to the cores in the cluster) we call L2.
When used standalone, we sometimes just use the name "TCDM" to refer to the same memory structure, and I am afraid this might cause a bit of confusion.
There are also references to SCM (Standard Cell based Memory), which is an (optional) additional part of the memory mapped to latch/FF arrays and are therefore operational at lower voltages than regular memory cuts we have access to.
As for simulation, we suggest to use the SDK for that. The linker defines that moves your core/data to the correct address are already correctly configured for the versions that you check out, handling the lower level details for you.
We are working towards better documentation that should also help with lower level access, but these take time. We are always happy to receive contributions to documentations and clarifications. Simply start a pull request on the GitHub
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