PULP is a silicon-proven Parallel Ultra Low Power platform targeting high energy efficiencies. The platform is organized in clusters of RISC-V cores that share a tightly-coupled data memory. It consists of a set of IPs described in the SystemVerilog hardware description language (HDL), the related simulation and synthesis scripts, as well as the runtime software written in C and RISC-V assembly to enable using the platform.
Both PULPino and PULPissimo contain only a single RISC-V core, there is no multi-core support. This means that most of the memory and cache sharing infrastructure in multi-core PULP systems isn't needed for these smaller systems. PULPissimo ('the ultimate PULP') is a more advanced and a more complex architecture compared to PULPino ('the small PULP'). PULPissimo, among other things, includes the support to allow peripherals to copy data directly to memory using a µDMA. PULPino and PULPissimo are microprocessor systems intended for direct use and contain most of the interfaces we have developed throughout the PULP project.
There are several ways you can contribute to the PULP project. Even though we have tested PULP extensively and still continue to do so, we can not guarantee that there are no issues left in the system. Therefore, you can contribute by reporting issues and limitations and by proposing fixes via the PULPino GitHub issue manager or via our mailing list (see FAQ item below). This allows us to maintain the platform and make it better and more flexible. The source code is freely accessible, so it's easy to see the changes.
Moreover, as PULP is a research-driven project, we routinely propose semester and master thesis projects at ETH Zurich and at the University of Bologna. Contact us in case you are interested.
You can design your own PULP chips, however, we cannot release any technology-specific views and information. Therefore, you will have to make adjustments to the code in order to instantiate the appropriate SRAM (or Flash) macros, I/O cells and clocking solution (PLL/FLL) to the specific technology you are using. We have successfully manufactured and used PULP based chips in the following technologies:
We have one mailing list to share new developments and listen to change requests. You can subscribe to it by sending mail to:
The bulk of the PULP platform, i.e. the HDL design of its IPs, the related simulation and synthesis scripts and the IP documentation, is under the copyright of ETH Zurich and the University of Bologna and is released under the Solderpad Hardware License, a liberal open-source license derived from the Apache License Version 2.0. Most development tools we developed and software that runs on the PULP platform is released under liberal open-source licenses such as 3-clause BSD. Specialized toolchains and debug tools based on GCC are copyright of the Free Software Foundation and released under the GNU GPLv3 license.
The PULP platform is open-source and free and is meant to be used by other research institutes, universities, and companies. You can download it, use it directly or modify it as you see fit. PULP is released under the Solderpad Hardware License, which allows commercial use and does not impose any constraints on additional IPs that you develop and connect to the platform. You do not need an additional permission from us. We would appreciate if you let us know in case you use PULP in your research projects or commercial projects. We kindly ask you to cite the relevant scholarly publications.
ETH Zurich and University of Bologna are academic institutions, and we manufacture our ASICs (see Silicon Proven designs) only in prototype quantities using Multi Project Waver runs. We do have small quantities of test and demo boards that we make available to our project partners, but the licenses we use for developing the chips will not allow us to make them available commercially. Good news is that there are companies that design, manufacture and sell PULP based chips. Greenwaves Technologies has developed its GAP8 IoT processor based on our multi-core PULP system, and has development boards for sale. We hope that in the near future there will be more companies offering PULP-based chips.
The bulk of the PULP platform is implemented using the synthesizable subset of the SystemVerilog hardware description language. The software running on PULP/PULPino is written in RISC-V assembly and in C. The code running on the multi-core PULP can use the OpenMP programming model to facilitate parallel programming. Development tools and scripts are written in a variety of languages such as C, Python, C++, TCL, and shell scripts.
We mainly used ModelSim/QuestaSim for simulation, which is also supported by our automatic script generation tools for the IPs. We currently cannot provide support for other simulation environments, however, the platform should work on any simulation tool that is able to understand synthesizable SystemVerilog. If you can provide patches to extend support for other simulation tools, we’ll be happy to review them and if applicable, merge them in.
We targeted predominantly Xilinx FPGAs and used Xilinx Vivado for FPGA synthesis, eventhough we are aware of the fact that it is also possible to use Synopsys Synplify with some minor changes. We don’t expect significant problems with porting the platform to other FPGA vendors provided they support SystemVerilog as a source HDL, with the exception of adaptation of some of the IPs. Regarding the synthesis for ASIC targets, we mainly use Synopsys Design Compiler. However, we expect other synthesis tools to work as well, provided they support SystemVerilog.