Moderated By: Moderators, Super Moderators
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PULP General questions
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| Thread / Author | Replies | Views [desc] | Last Post | ||
Compiling and running CNNs on FPGA(pulp)
04-04-2024, 12:33 AM
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2 | 7,269 |
04-11-2024, 12:29 PM Last Post: NEO |
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Issues booting HERO in ZCU102
02-28-2023, 08:26 AM
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1 | 7,303 |
04-18-2023, 03:37 PM Last Post: pedro.lobo |
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GCC Compiler output
01-14-2020, 11:29 AM
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0 | 7,342 |
01-14-2020, 11:29 AM Last Post: HariniM |
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Accelerator HWPE Example Loops on ZedBoard
04-20-2020, 02:21 PM
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0 | 7,346 |
04-20-2020, 02:21 PM Last Post: acastillo |
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which spike version for ri5cy?
06-11-2019, 02:52 PM
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0 | 7,425 |
06-11-2019, 02:52 PM Last Post: etayke |
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pulp-soc-defines.sv
04-18-2019, 08:17 AM
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0 | 7,432 |
04-18-2019, 08:17 AM Last Post: MikkeN |
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FPGA - Booting (.bit + .elf) from flash or SD card
02-18-2020, 07:37 AM
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0 | 7,454 |
02-18-2020, 07:37 AM Last Post: AhmedZaky |
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New SoC configuration for SDK
10-01-2019, 09:19 AM
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0 | 7,459 |
10-01-2019, 09:19 AM Last Post: MarekPikula |
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Pulpissimo synthesis error
05-23-2019, 11:25 AM
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0 | 7,468 |
05-23-2019, 11:25 AM Last Post: MikkeN |
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Changing pulpissimo memory layout
08-27-2019, 09:45 AM
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0 | 7,525 |
08-27-2019, 09:45 AM Last Post: anfevp |
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Integrating NVDLA with PULPissimo
06-13-2019, 04:17 PM
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0 | 7,550 |
06-13-2019, 04:17 PM Last Post: AhmedZaky |
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[PULPissimo] How to resize memory correctly
12-16-2019, 02:21 AM
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0 | 7,567 |
12-16-2019, 02:21 AM Last Post: gideros |
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Compiler behaves unexpectedly
02-13-2020, 03:55 PM
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0 | 7,622 |
02-13-2020, 03:55 PM Last Post: ian |
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Using HAL headers in HERO project
06-03-2019, 11:46 AM
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0 | 7,645 |
06-03-2019, 11:46 AM Last Post: tmilkovic |
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How to build SDK for PULPino?
04-19-2019, 12:27 PM
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0 | 7,664 |
04-19-2019, 12:27 PM Last Post: zhouqiang |
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PULPino JTAG access
08-22-2019, 02:15 PM
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0 | 7,751 |
08-22-2019, 02:15 PM Last Post: MarekPikula |
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Multi Core PULP first time setup
12-25-2024, 05:53 PM
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2 | 7,768 |
06-09-2026, 07:17 AM Last Post: calimi |
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Error on Macro 'DMI_JTAG_IDCODE is not defined when built pulp RTL simulation pfm
06-21-2019, 05:09 PM
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0 | 7,793 |
06-21-2019, 05:09 PM Last Post: mapletree |
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RI5CY - FPGA Synthesis
05-07-2019, 03:20 PM
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0 | 7,806 |
05-07-2019, 03:20 PM Last Post: jaypi |
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Difference between RI5CY and CV32E40P
09-24-2024, 02:37 AM
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2 | 7,921 |
09-27-2024, 06:17 AM Last Post: eureka |
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