If you are adding your own RTL description to an existing PULPino environment, you need to make sure that the new files are also somehow integrated to the build flow. This can be done by writing your scripts (not so difficult) or adapting the present scripts so that they also take into account the files that contain your description.
For example, for the Questasim simulation, you would use the following script:
https://github.com/pulp-platform/pulpino...tl_sim.csh
which will then call a number of scripts such as:
https://github.com/pulp-platform/pulpino...pulpino.sh
which has individual lines to compile parts such as
vlog -quiet -sv -work ${LIB_PATH} +incdir+${RTL_PATH}/includes ${ASIC_DEFINES} ${CORE_DEFINES} ${RTL_PATH}/pulpino_top.sv
These files do not update automatically (it is not that easy to do properly). If you want, you can add the lines to compile your parts in these scripts as well. For each tool (FPGA compilation, ASIC mapping etc) you would need to do the same.
Just a word of caution, modifying your own processor is a fairly involved process. While our releases help, you still need to have the background and experience with the design tools you are using to be successful.