Pulpissimo bitstream generation.

[meggiman]

Hi meggi,

Thank you very much on your help with OpenOCD. By the way, do you have any idea how to integrate 3rd party module into PULPissimo via AXI interface? I have tried connect it to AXI interface in the top level of pulp_soc (which is used for cluster) and soc_interconnect but both of them don't work.

Thank you in advance.
Dao

Hi gideros,

In theory it should work straight out of the box if you connect the currently dangling ports in the toplevel pulpissimo.sv. You find the address of the AXI plug in ips/pulp_soc/rtl/pulp_soc/soc_interconnect.sv on line 260 and 261 (base address: 0x1000_0000, end_address: 0x1040_0000). For reference you should have a look at https://github.com/pulp-platform/pulp. In this project PULPissimo is connected to an 8 core cluster connected on the AXI plug. This should give you an idea on how to connect your 3rd party module. Most of our own accelerators we developed so far were integrated by directly connecting them to the TCDM bus to get direct access to the shared memory.

Greetings,
Manuel

[AhmedZaky]

Hey,

I am stuck also at that error " openocd: src/target/riscv/riscv.c:2530: riscv_set_current_hartid: Assertion `riscv_hart_enabled(target, hartid)' failed. ", I've read the comments but I couldn't locate that patched openocd that comes with the SDK. May you please elaborate more one this  ?

Thanks !

Hi AhmedZaky,

I just realized that the patched Openocd is not installed by default if you do not have access to the artifactory server (file server at ETH that contains precompiled binaries). However 
I revised the README in the fpga branch and added some sections on how to install the patched OpenOCD from source. Please follow the instructions at https://github.com/pulp-platform/pulpiss...nd-openocd.

Hey Thanks for your reply, I already applied the patch manually to the source file of openocd and it works. 

Noe wen I try to either run the example the FPGA or trying to debug I got the following errors: 

1- When I am trying to run the example directly without debugging using the " make run" command: 


"/pulp-sdk/pkg/sdk/dev/install/ws/python/runner/fpga/pulpissimo/elf_run.gdb:1: Error in sourced command file:  localhost:3333: Connection timed out" 

2- when I try to use the debugger by running three terminals at the same time " openocd, GDB and screen / minicom" I face the following issue: 

            - Minicom: I receive nothing from minicom, and I am assigning the right USB port hopefully. 
            - Screen: I receive odd characters instead of the real message. 

Could you please help on that ? What might be the problem ? 

Thanks so much !

[meggiman]

Hey,

I am stuck also at that error " openocd: src/target/riscv/riscv.c:2530: riscv_set_current_hartid: Assertion `riscv_hart_enabled(target, hartid)' failed. ", I've read the comments but I couldn't locate that patched openocd that comes with the SDK. May you please elaborate more one this  ?

Thanks !

Hi AhmedZaky,

I just realized that the patched Openocd is not installed by default if you do not have access to the artifactory server (file server at ETH that contains precompiled binaries). However 
I revised the README in the fpga branch and added some sections on how to install the patched OpenOCD from source. Please follow the instructions at https://github.com/pulp-platform/pulpiss...nd-openocd.

Hey Thanks for your reply, I already applied the patch manually to the source file of openocd and it works. 

Noe wen I try to either run the example the FPGA or trying to debug I got the following errors: 

1- When I am trying to run the example directly without debugging using the " make run" command: 


"/pulp-sdk/pkg/sdk/dev/install/ws/python/runner/fpga/pulpissimo/elf_run.gdb:1: Error in sourced command file:  localhost:3333: Connection timed out" 

2- when I try to use the debugger by running three terminals at the same time " openocd, GDB and screen / minicom" I face the following issue: 

            - Minicom: I receive nothing from minicom, and I am assigning the right USB port hopefully. 
            - Screen: I receive odd characters instead of the real message. 

Could you please help on that ? What might be the problem ? 

Thanks so much !

Unless you connected the second micro-USB cable for the UART to the wrong connector on the Genesys2 board the most likely reason is that you set the wrong frequency (or even forgot to specify it at all) for the core and peripheral clock in your application which results in a different baudrate (see FPGA section in README). The default frequency currently mentioned in the README relates to the most recent version of PULPissimo. Depending at which commit you generated the bitstream the frequency might be a different one since I only recently changed them to higher values (the mentioned 40 MHz and 20 MHz). You can either pull the latest commits on the FPGA branch and regenerate the bitstream or check the timing summary in vivado to figure out which frequencies are actually used with your current bitstream. In any case you must set the frequency in your application since at the moment the SDK does not assume any reasonable defaults (most likely we will change that in the future).  

Regarding the 'make run' target: The runner script for the FPGA is still unstable and occasionally does not work due to timing problems when starting the OpenOCD server, gdb and the minicom session. For the moment I recommend to use OpenOCD and gdb manually as documented in the first part of the README. This approach so far worked reliably for me and has the additional benefit that you can debug your application or even the runtime initialization before entering main() with gdb.

[zealshah29]

Hi naprpo,

First of all, there is another detail I forgot to mention in the README (I will revise it and try to document it better for future users):
You need to tell the SDK which frequency PULPissimo is running with so the SDK can configure the right value for the UART's clock divider. Otherwise the baudrate will be wrong.
In order to do so define the following global variables in you source code:

int __rt_fpga_fc_frequency = 40000000;
int __rt_fpga_periph_frequency = 20000000;

If you didn't change anything in the bitstream generation script these two lines should configure the SDK to use the frequencies of 40MHz for the Core and 20MHz for the SoC that are used by default during Synthesis.

However, since you don't see any output at all (even with the wrong frequency breakpoints should work), there is probably another issue with your binary. ( I just successfully tried it with commit id 3256fe7, BTW: I suppose you didn't forget to run make on the SDK after checkout and sourced again configs/pulpissimo.sh and configs/fpgas/pulpissimo/genesys2.sh before recompilation of the SDK and the binary?). Could you send me the source code, the disassembly (run 'make dis>test.S') and the compiled elf binary so I can try it myself?

Hi meggiman,

Thanks for the help. I had the issues with SDK buid.
It is working now.

Regards,
naprpo

Hi napropo, could you let me know that what was the issue that you were facing with sdk build and how did you solve it? Because I am stuck on the same step, i.e, "continuing" on gdb terminal, and haven't been able to figure out any fixes so far. Thanks.