QuestaSim Installation for RTL Simulation

[achen9]

Hello,

I am new to RTL simulations, and I noticed that many of the PULP platforms appear to require QuestaSim in order to conduct them, but I am not too familiar with RTL environment setups. Specifically, I am currently working with HERO and Pulpissimo. 

I was wondering if anyone has any pointers or recommendations on where to look for instructions to set up a complete QuestaSim environment from scratch. The machine I am running on is CentOS 7.

Thank you very much in advance.

[kgf]

Hello,

Questasim is a commercial EDA tool from Siemens/Mentor. It comes with an installation tool and plenty of documentation as well as support. If you are in academia, there are academic programs your institution can take advantage of to get access to it. As a company you will have to acquire a license (and pay). Unfortunately if you are an unaffiliated individual there are fewer options. 

Technically PULP does not require a specific simulator (i.e. Questasim), but we know our code runs when we use this simulator. Other commercial simulators (VCS, ncsim/xcellium, aldec etc..) should in theory all work.. There are also open source RTL simulators like verilator. 

The practical reality is that there are still some SystemVerilog constructs that one or the other simulator does not support (or has difficulties) which can cause issues (verilator for example does not support assertions) with the code as it is written. None of it is a serious problem, given some time the code can be cleaned up (or simplified), newer versions of the tools have better support reducing these issues, at the very worst, simulator specific IFDEFs can be added. BUT, we state that we use Questasim, so that people are aware with which simulator we usually work (we also ended up using both VCS and xcellium in different projects) meaning that we cleaned it up to make sure it will work with Questasim.  

We are moving more and more to have code that supports Verilator, but again, the code base is large, and there are could still be some bits and pieces that needs to be cleaned up for Verilator. As this is an open source project, this is also where contributions are needed, we are happy to accept PR for fixes for compatibility issues of simulators. 

Hope that helps
KGF

[achen9]

Hello,

Questasim is a commercial EDA tool from Siemens/Mentor. It comes with an installation tool and plenty of documentation as well as support. If you are in academia, there are academic programs your institution can take advantage of to get access to it. As a company you will have to acquire a license (and pay). Unfortunately if you are an unaffiliated individual there are fewer options. 

Technically PULP does not require a specific simulator (i.e. Questasim), but we know our code runs when we use this simulator. Other commercial simulators (VCS, ncsim/xcellium, aldec etc..) should in theory all work.. There are also open source RTL simulators like verilator. 

The practical reality is that there are still some SystemVerilog constructs that one or the other simulator does not support (or has difficulties) which can cause issues (verilator for example does not support assertions) with the code as it is written. None of it is a serious problem, given some time the code can be cleaned up (or simplified), newer versions of the tools have better support reducing these issues, at the very worst, simulator specific IFDEFs can be added. BUT, we state that we use Questasim, so that people are aware with which simulator we usually work (we also ended up using both VCS and xcellium in different projects) meaning that we cleaned it up to make sure it will work with Questasim.  

We are moving more and more to have code that supports Verilator, but again, the code base is large, and there are could still be some bits and pieces that needs to be cleaned up for Verilator. As this is an open source project, this is also where contributions are needed, we are happy to accept PR for fixes for compatibility issues of simulators. 

Hope that helps
KGF

Thank you for your timely response. It appears that I do not have access to QuestaSim, but we do have Xcelium. As such, I tried to build the RTL simulation platform for Pulpissimo, which is said to have Xcelium support on its github page. However, when I tried to run make, I am still running into an abundance of errors that seem to suggest that it is still trying to run QuestaSim commands through the usage of vsim. The errors are as follows:

Code:

make checkout
find: 'work': No such file or directory
./bender checkout
touch Bender.lock
make scripts
find: 'work': No such file or directory
make[1]: Entering directory `/home_local/[LOCALE]/pulpissimo'
echo 'set ROOT [file normalize [file dirname [info script]]/..]' > sim/compile.tcl
./bender script vsim \
       --vlog-arg="-suppress 2583 -suppress 13314 \"+incdir+\$ROOT/rtl/includes\"" --vcom-arg="" \
       -t rtl -t test \
       | grep -v "set ROOT" >> sim/compile.tcl
mkdir -p fpga/pulpissimo/tcl/generated
./bender script vivado -t fpga -t xilinx > fpga/pulpissimo/tcl/generated/compile.tcl
make[1]: Leaving directory `/home_local/[LOCALE]/pulpissimo'

Code:

make build
find: 'work': No such file or directory
cd sim && make all
make[1]: Entering directory `/home_local/[LOCALE]/pulpissimo/sim'
make -C ../rtl/tb/remote_bitbang all
make[2]: Entering directory `/home_local/[LOCALE]/pulpissimo/rtl/tb/remote_bitbang'
cc -MT remote_bitbang.o -MMD -MP -MF ./.d/remote_bitbang.Td -std=gnu11 -fno-strict-aliasing -Wall -Wextra -Wno-missing-field-initializers -Wno-unused-function -Wno-missing-braces -O2 -g -march=native -DENABLE_LOGGING -DNDEBUG -fPIC -I./  \
       -c  remote_bitbang.c -o remote_bitbang.o
ld -shared -E --exclude-libs ALL -o librbs.so  \
       remote_bitbang.o sim_jtag.o
make[2]: Leaving directory `/home_local/[LOCALE]/pulpissimo/rtl/tb/remote_bitbang'
vsim -c -do 'source compile.tcl; quit'
make[1]: vsim: Command not found
make[1]: *** [build] Error 127
make[1]: Leaving directory `/home_local/[LOCALE]/pulpissimo/sim'
make: *** [build] Error 2

Is there some sort of variable or path that I'm supposed to be setting in order for it to run with Xcelium? How should I proceed in this case?

Thank you in advance.

[xinhuliu]

Hello,

Questasim is a commercial EDA tool from Siemens/Mentor. It comes with an installation tool and plenty of documentation as well as support. If you are in academia, there are academic programs your institution can take advantage of to get access to it. As a company you will have to acquire a license (and pay). Unfortunately if you are an unaffiliated individual there are fewer options. 

Technically PULP does not require a specific simulator (i.e. Questasim), but we know our code runs when we use this simulator. Other commercial simulators (VCS, ncsim/xcellium, aldec etc..) should in theory all work.. There are also open source RTL simulators like verilator. 

The practical reality is that there are still some SystemVerilog constructs that one or the other simulator does not support (or has difficulties) which can cause issues (verilator for example does not support assertions) with the code as it is written. None of it is a serious problem, given some time the code can be cleaned up (or simplified), newer versions of the tools have better support reducing these issues, at the very worst, simulator specific IFDEFs can be added. BUT, we state that we use Questasim, so that people are aware with which simulator we usually work (we also ended up using both VCS and xcellium in different projects) meaning that we cleaned it up to make sure it will work with Questasim.  

We are moving more and more to have code that supports Verilator, but again, the code base is large, and there are could still be some bits and pieces that needs to be cleaned up for Verilator. As this is an open source project, this is also where contributions are needed, we are happy to accept PR for fixes for compatibility issues of simulators. 

Hope that helps
KGF

Thank you for your timely response. It appears that I do not have access to QuestaSim, but we do have Xcelium. As such, I tried to build the RTL simulation platform for Pulpissimo, which is said to have Xcelium support on its github page. However, when I tried to run make, I am still running into an abundance of errors that seem to suggest that it is still trying to run QuestaSim commands through the usage of vsim. The errors are as follows:

Code:

make checkout
find: 'work': No such file or directory
./bender checkout
touch Bender.lock
make scripts
find: 'work': No such file or directory
make[1]: Entering directory `/home_local/[LOCALE]/pulpissimo'
echo 'set ROOT [file normalize [file dirname [info script]]/..]' > sim/compile.tcl
./bender script vsim \
       --vlog-arg="-suppress 2583 -suppress 13314 \"+incdir+\$ROOT/rtl/includes\"" --vcom-arg="" \
       -t rtl -t test \
       | grep -v "set ROOT" >> sim/compile.tcl
mkdir -p fpga/pulpissimo/tcl/generated
./bender script vivado -t fpga -t xilinx > fpga/pulpissimo/tcl/generated/compile.tcl
make[1]: Leaving directory `/home_local/[LOCALE]/pulpissimo'

Code:

make build
find: 'work': No such file or directory
cd sim && make all
make[1]: Entering directory `/home_local/[LOCALE]/pulpissimo/sim'
make -C ../rtl/tb/remote_bitbang all
make[2]: Entering directory `/home_local/[LOCALE]/pulpissimo/rtl/tb/remote_bitbang'
cc -MT remote_bitbang.o -MMD -MP -MF ./.d/remote_bitbang.Td -std=gnu11 -fno-strict-aliasing -Wall -Wextra -Wno-missing-field-initializers -Wno-unused-function -Wno-missing-braces -O2 -g -march=native -DENABLE_LOGGING -DNDEBUG -fPIC -I./  \
       -c  remote_bitbang.c -o remote_bitbang.o
ld -shared -E --exclude-libs ALL -o librbs.so  \
       remote_bitbang.o sim_jtag.o
make[2]: Leaving directory `/home_local/[LOCALE]/pulpissimo/rtl/tb/remote_bitbang'
vsim -c -do 'source compile.tcl; quit'
make[1]: vsim: Command not found
make[1]: *** [build] Error 127
make[1]: Leaving directory `/home_local/[LOCALE]/pulpissimo/sim'
make: *** [build] Error 2

Is there some sort of variable or path that I'm supposed to be setting in order for it to run with Xcelium? How should I proceed in this case?

Thank you in advance.

Hi, 

I am setting up the environment of pulpissimo, when I run the "make checkout" command, it shows the same error as yours. Do you fix it now?
Because I haven't downloaded QuesaSim on my Ubantu, am I needed to download QuestaSim to run the "make checkout" command, or can I skip this command in other ways?

Thanks in advance!

[kgf]

Hi, 

I am setting up the environment of pulpissimo, when I run the "make checkout" command, it shows the same error as yours. Do you fix it now?
Because I haven't downloaded QuesaSim on my Ubantu, am I needed to download QuestaSim to run the "make checkout" command, or can I skip this command in other ways?

Thanks in advance!

I believe you are following the instructions under:
  https://github.com/pulp-platform/pulpiss...n-platform

That one is for running RTL simulation, so you would need one or the other RTL simulation program. You do not have to run RTL simulation you can also develop code that would run on the platform through the 'simple runtime', in that case you do not need this step and 'skip' it as you say.  However most people interested in PULPissimo (at some point) would also want to simulate the HW, so they would need this step, and need a simulator.

[xinhuliu]

Hi, 

I am setting up the environment of pulpissimo, when I run the "make checkout" command, it shows the same error as yours. Do you fix it now?
Because I haven't downloaded QuesaSim on my Ubantu, am I needed to download QuestaSim to run the "make checkout" command, or can I skip this command in other ways?

Thanks in advance!

I believe you are following the instructions under:
  https://github.com/pulp-platform/pulpiss...n-platform

That one is for running RTL simulation, so you would need one or the other RTL simulation program. You do not have to run RTL simulation you can also develop code that would run on the platform through the 'simple runtime', in that case you do not need this step and 'skip' it as you say.  However most people interested in PULPissimo (at some point) would also want to simulate the HW, so they would need this step, and need a simulator.

Thank u for replying, that's very clear!

[CongHuang]

Hello,

Questasim is a commercial EDA tool from Siemens/Mentor. It comes with an installation tool and plenty of documentation as well as support. If you are in academia, there are academic programs your institution can take advantage of to get access to it. As a company you will have to acquire a license (and pay). Unfortunately if you are an unaffiliated individual there are fewer options. 

Technically PULP does not require a specific simulator (i.e. Questasim), but we know our code runs when we use this simulator. Other commercial simulators (VCS, ncsim/xcellium, aldec etc..) should in theory all work.. There are also open source RTL simulators like verilator. 

The practical reality is that there are still some SystemVerilog constructs that one or the other simulator does not support (or has difficulties) which can cause issues (verilator for example does not support assertions) with the code as it is written. None of it is a serious problem, given some time the code can be cleaned up (or simplified), newer versions of the tools have better support reducing these issues, at the very worst, simulator specific IFDEFs can be added. BUT, we state that we use Questasim, so that people are aware with which simulator we usually work (we also ended up using both VCS and xcellium in different projects) meaning that we cleaned it up to make sure it will work with Questasim.  

We are moving more and more to have code that supports Verilator, but again, the code base is large, and there are could still be some bits and pieces that needs to be cleaned up for Verilator. As this is an open source project, this is also where contributions are needed, we are happy to accept PR for fixes for compatibility issues of simulators. 

Hope that helps
KGF

Hi, I am currently working on RTL simulation of Pulpissimo as well.

I have installed rust and installed bender (cargo install bender --version 0.25.2) following the instructions on https://github.com/pulp-platform/bender.

Then I typed "make checkout" in the teriminal, and it turns out as follows:

find: `work': No such file or directory
./bender checkout
bash: ./bender: Permission denied
make: *** [checkout] Error 126

Could you please kindly tell me the possible reasons and how to fix it? Thanks in advance.

Cong Huang

[kgf]

I think we need to update the description a little bit. It seems to be confusing.

The
find: `work': No such file or directory

is not really the issue. Do not worry about that that much (we should fix that it appears, but that is not what is causing the problem).

Before you start, make sure
- executables for Modelsim (or other simulator) are in your search path.. i.e. if you type vlog (for Modelsim/Questasim) on the command line it will work.
- seems like the script was tested with bash as the shell (maybe some others as well). At least I had some issues with csh.. You seem to have 'bash' as one of your error lines suggests it. So in your case this should be OK.

The
./bender checkout

part is strange.. once you download bender (part of the make checkout) it should have been installed with execute permissions. I guess, the script is not checking this properly and assumes this is the case. If your setup has a umask that prevents created files to be executable this could cause the issue.. See the permissions of bender
ls -l bender

And if you see it is not executable (something like -rwxr-xr-x) you can change this by
chmod 755 bender

should fix the issue.

[CongHuang]

I think we need to update the description a little bit. It seems to be confusing.

The
 find: `work': No such file or directory

is not really the issue. Do not worry about that that much (we should fix that it appears, but that is not what is causing the problem).

Before you start, make sure
- executables for Modelsim (or other simulator) are in your search path.. i.e. if you type vlog (for Modelsim/Questasim) on the command line it will work.
- seems like the script was tested with bash as the shell (maybe some others as well). At least I had some issues with csh.. You seem to have 'bash' as one of your error lines suggests it. So in your case this should be OK.

The
 ./bender checkout

part is strange.. once you download bender (part of the make checkout) it should have been installed with execute permissions. I guess, the script is not checking this properly and assumes this is the case. If your setup has a umask that prevents created files to be executable this could cause the issue.. See the permissions of bender
 ls -l bender

And if you see it is not executable (something like -rwxr-xr-x) you can change this by
 chmod 755 bender

should fix the issue.

Hi, thank you for your timely reply!

I have tested by typing vlog, and Modelsim/Questasim is executable.
The problem I mentioned above has been solved with your solution (chmod 755 bender).

However, it seems that I encountered other problems when I typed "make checkout". It turns out as follows:

Code:

./bender checkout
touch Bender.lock
make scripts
make[1]: Entering directory `/workspace/home/huangcong/pulpissimo'
echo 'set ROOT [file normalize [file dirname [info script]]/..]' > sim/compile.tcl
./bender script vsim \
        --vlog-arg="-suppress 2583 -suppress 13314 \"+incdir+\$ROOT/rtl/includes\"" --vcom-arg="" \
        -t rtl -t test \
        | grep -v "set ROOT" >> sim/compile.tcl
make[1]: *** [scripts-bender-vsim] Error 1
make[1]: Leaving directory `/workspace/home/huangcong/pulpissimo'
make: *** [checkout] Error 2

When I typed "make build", the error code is:

Code:

cd sim && make all
make[1]: Entering directory `/workspace/home/huangcong/pulpissimo/sim'
make -C ../rtl/tb/remote_bitbang all
make[2]: Entering directory `/workspace/home/huangcong/pulpissimo/rtl/tb/remote_bitbang'
cc -MT remote_bitbang.o -MMD -MP -MF ./.d/remote_bitbang.Td -std=gnu11 -fno-strict-aliasing -Wall -Wextra -Wno-missing-field-initializers -Wno-unused-function -Wno-missing-braces -O2 -g -march=native -DENABLE_LOGGING -DNDEBUG -fPIC -I./  \
        -c  remote_bitbang.c -o remote_bitbang.o
ld -shared -E --exclude-libs ALL -o librbs.so  \
        remote_bitbang.o sim_jtag.o
make[2]: Leaving directory `/workspace/home/huangcong/pulpissimo/rtl/tb/remote_bitbang'
vsim -c -do 'source compile.tcl; quit'
/eda/mentor/questa_10.4/questasim/bin/../linux/vish: error while loading shared libraries: libXft.so.2: cannot open shared object file: No such file or directory
make[1]: *** [build] Error 127
make[1]: Leaving directory `/workspace/home/huangcong/pulpissimo/sim'
make: *** [build] Error 2

I really have no clues how to fix the problems (as I am not familiar with Modelsim/Questasim simulation) . 
Could you please offer me some advice? Thank you!

[kgf]

If I were to guess, this would be an older Questasim/Modelsim. Most probably one that comes packaged with Altera/Intel (as that one seems to be somehow available). You will need a proper and relatively recent installation. Try
vlog -version

if this is something from 2019 or newer it should be OK.. (older version can also work) Then the problem is somewhere else, but the error message suggests that the vlog script did not work properly.

I know it sounds a bit elitist, but if you are planning on running RTL simulations and make changes/modifications at RTL level, you will need to get more familiar with the tools associated with it.

On the other hand, maybe for what you want to do, RTL level simulations may be an overkill, and you might want to use the virtual platform. We even have an image ready with teh GVSoC platform on the https://pulp-platform.org/pulp_training.html training page.