Welcome to the PULP Training page! You can now find all the important slides and videos recorded during our training sessions here and in this way get acquainted with the many faces of the PULP Platform.
We have more material in the queue and are going to publish it in the course of March 2021.
In this tutorial, Nazareno introduces the Software Development Kit for PULP, while Giuseppe elaborates on the GCC Compilation Toolchain.
|Part 1||Part 2|
|Structure (RTOS, ARCHI, HAL, tools)||Introduction to the GCC compilation toolchain|
|How to include a new target (makefile)||Toolchain components|
|How to customize a target (number of cores, memory)||Downloading and building the toolchain|
|PMSIS: common structure for device (cluster/ram): device struct, config, open, task, close||RISC-V / PULP specific options|
|-||Performance-driven optimization techniques|
Slides Part 1: Nazareno Bruschi PULP SDK and PMSIS
Slides Part 2: Giuseppe Tagliavini Mastering the PULP GCC toolchain
Robert and Manuel instruct you on HW/SW Development with PULP in the course of a two-day training.
|Day 1||Day 2|
|PULPissimo SoC Architecture||FPGA Port|
|Software Environment||PULP IP Landscape|
|RTL Development Flow||Hands-on Full-stack IP Integration Exercise|
|RTL Simulation||PULPIssimo Memory Layout Modification|
Listen to our instructors Nazareno and Alessio talking about the PULP Virtual Platform and DORY our automated tool to deploy DNNs on memory constrained devices.
VM Image with all tools ready: Download Caution 8.5 GB
Slides Part 1: Nazareno Bruschi PULP Simulator and SDK
Slides Part 2: Alessio Burello Deployment of DNN on Extreme Edge Devices (1)
In this tutorial, Davide explains the architecture of PULPissimo, the differences among individual PULP cores, Xpulp extensions and much more.