05-08-2019, 12:53 PM
Clock problem when writing sdc file in order to synthesize PULPino
I am now trying to write a constraint file (sdc file) to synthesize PULPino （using DC）, but I don't know much about PULPino's RTL design， so it is a challenging task for me，my question is：
1. According to the .xdc file in vivado, I infer that PULPino has three asynchronous clocks clk, spi_clk_i, tck_i. What is the frequency relationship between them?
2. In DC, I use the command get_nets/ports *clk*, I also got a spi_master_clk_o, which looks like an output port. What is it used for? Do I need to constrain it?
3. In the ASIC design, I want to set the frequency of the main clock clk to 100MHz. So, how should I set the frequency for the other two clocks?
4. In addition, I also want to constrain the generated clock. Is there a generated clock in PULPino? How should I find out all the generated clocks and the corresponding source clock?
I am now trying to write a constraint file (sdc file) to synthesize PULPino （using DC）, but I don't know much about PULPino's RTL design， so it is a challenging task for me，my question is：
1. According to the .xdc file in vivado, I infer that PULPino has three asynchronous clocks clk, spi_clk_i, tck_i. What is the frequency relationship between them?
2. In DC, I use the command get_nets/ports *clk*, I also got a spi_master_clk_o, which looks like an output port. What is it used for? Do I need to constrain it?
3. In the ASIC design, I want to set the frequency of the main clock clk to 100MHz. So, how should I set the frequency for the other two clocks?
4. In addition, I also want to constrain the generated clock. Is there a generated clock in PULPino? How should I find out all the generated clocks and the corresponding source clock?