12-02-2020, 10:46 AM
Did you try running a RTL simulation first?
If that works then make sure you followed the steps on GitHub and source the right files before compiling an App for FPGA.
After loading the program to L2 you should set a breakpoint.
So basically in gdb you do:
1) load
2) b exit
3) continue
Did you have any output on minicom or screen?
If that works then make sure you followed the steps on GitHub and source the right files before compiling an App for FPGA.
After loading the program to L2 you should set a breakpoint.
So basically in gdb you do:
1) load
2) b exit
3) continue
Did you have any output on minicom or screen?