12-28-2021, 11:59 AM
Hello, team!
I am currently working on a project related to PULPino. I am wondering how to put the core in the IDLE state. The datasheet introduces an apb_event_unit for clock gating everything else and waking up the core if an event/interrupt arrives. I notice there is another peripheral, apb_pulpino contains CLK Gate as well.
However, while running benchmarks such as hello/fft/sha/fir, I could not find the situations when the core is in the IDLE state. In other words, the clock signal is not gated during the entire operation. Is the clock gating function being enabled? Is there any benchmark I can use to test the clock gating (it would be better if the riscv-core and peripherals can be clock gated simultaneously)?
Thanks for your kind reply！
I am currently working on a project related to PULPino. I am wondering how to put the core in the IDLE state. The datasheet introduces an apb_event_unit for clock gating everything else and waking up the core if an event/interrupt arrives. I notice there is another peripheral, apb_pulpino contains CLK Gate as well.
However, while running benchmarks such as hello/fft/sha/fir, I could not find the situations when the core is in the IDLE state. In other words, the clock signal is not gated during the entire operation. Is the clock gating function being enabled? Is there any benchmark I can use to test the clock gating (it would be better if the riscv-core and peripherals can be clock gated simultaneously)?
Thanks for your kind reply！