Ariane Performance Measures
This is from Florian (who is not yet on the board):

Ariane currently hardwires `[m|s]counteren` (`rdcycle` is a pseudo op for `csrr cycle`): "When the CY, TM, IR, or HPMn bit in the mcounteren register is clear, attempts to read the cycle, time, instret, or hpmcountern register while executing in S-mode or U-mode will cause an illegal instruction exception." Volume II: RISC-V Privilegd Architecture V1.12-draft, p. 35

Solution 1: Implement a trap handler in machine-mode software (probably `bbl`) which handles the illegal instruction (csr read) and reads from `mcycle` and reports back the result. Most of the trap handling infrastructure is already in place of the clint.

Solution 2: Implement `[m|s]counteren` which makes the bits readable in lower privilege levels. You need to make sure that machine mode software and supervisor mode software make them accessible.

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Messages In This Thread
Ariane Performance Measures - by jthoma - 11-12-2019, 08:08 AM
RE: Ariane Performance Measures - by kgf - 11-12-2019, 10:50 AM

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