Question about bitstream generation
#1
Hi, I'm new to this and got some errors when generating the bitstream file.

The code I ran:
Code:
$ cd $COREVMCU/fpga
$ make clean_nexys rev=nexysA7-100T
$ make nexys rev=nexysA7-100T
After running the above codes, I got the following errors.
Code:
ERROR: [Synth 8-439] module 'xilinx_slow_clk_mngr' not found [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv:48]
ERROR: [Synth 8-6156] failed synthesizing module 'fpga_slow_clk_gen' [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/fpga_slow_clk_gen.sv:24]
ERROR: [Synth 8-6156] failed synthesizing module 'safe_domain' [/home/core-v-mcu/rtl/pulpissimo/safe_domain.sv:12]
ERROR: [Synth 8-6156] failed synthesizing module 'pulpissimo' [/home/core-v-mcu/rtl/pulpissimo/pulpissimo.sv:13]
ERROR: [Synth 8-6156] failed synthesizing module 'xilinx_pulpissimo' [/home/core-v-mcu/fpga/pulpissimo-nexys/rtl/xilinx_pulpissimo.v:22]


When I commented out the module, some other errors would come out, saying those modules are not found. I guess there're four of them, which are xilinx_clk_mngr, xilinx_slow_clk_mngr, xilinx_private_ram and xilinx_interleaved_ram. I'm not sure if those modules are supposed to be generated by myself, or where should I get and put them? Any comments would be appreciated. Thanks in advance!

Sincerely,
Zorro
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Question about bitstream generation - by zorrolee777 - 02-04-2021, 06:24 PM

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