Question about bitstream generation
Hi Zorro,

First of all, which project are you actually trying to generate a bitstream for? PULPissimo? PULP-open? If it is PULPissimo: Are there any other errors further up the command log? The make target is supposed to first generate these Xilinx IPs as individual projects for you before invoking the main FPGA target. All of these IPs have a dedicated make file to generate them in fpga/pulpissimo-nexys/ips (although they should be called automatically with the main 'nexys' target).


Messages In This Thread
RE: Question about bitstream generation - by meggiman - 02-11-2021, 12:41 PM

Forum Jump:

Users browsing this thread: 1 Guest(s)