Question about bitstream generation
(02-11-2021, 12:41 PM)meggiman Wrote: Hi Zorro,

First of all, which project are you actually trying to generate a bitstream for? PULPissimo? PULP-open? If it is PULPissimo: Are there any other errors further up the command log? The make target is supposed to first generate these Xilinx IPs as individual projects for you before invoking the main FPGA target. All of these IPs have a dedicated make file to generate them in fpga/pulpissimo-nexys/ips (although they should be called automatically with the main 'nexys' target).


Hello Manuel,

Thank you so much for your reply! I'm using PULPissimo, and didn't get any errors before this step. I check the path you mentioned and I did find the IPs there. Then I tried to run the makefile in the /fpga/pulpissimo-nexys/ips/xilinx_clk_mngr manually, but got this error massage: 

Setting environment variables for nexys board

make: *** No rule to make target 'nexys'.  Stop.

Does this mean there are some problems when setting up these Xilinx IPs? If so how should I solve this?


Messages In This Thread
RE: Question about bitstream generation - by zorrolee777 - 02-16-2021, 03:18 AM

Forum Jump:

Users browsing this thread: 1 Guest(s)