update to ri5cy core interrupt system and toolchain
#1
Hello!

I am investigating using the ri5cy core for a commercial application.
Quite some time ago I looked into the ri5cy core via the Embecosm githubu fork:
https://github.com/embecosm/ri5cy

This seems to (now) be a quite old version of the core (32 interrupt inputs, much different csr implementation).

So, I've updated my core payload with the latest ri5cy rtl build.

I now have problems with my prototype interrupt code.
In C I have:


in "main()" {
    set_csr (0x300, 0x00000009);            //enable interrupts?
    write_csr(0x305, my_isr);               // isr address?
   
    // big long delay
    for (int i=0;i<10000;i++) asm("NOP");

}

void __attribute__ ((interrupt())) my_isr (){
    *simresult = (unsigned short int) 0xF111;    // flag result
}

which gives me:
00000300 <my_isr>:
 300: ff010113           addi sp,sp,-16
 304: 00f12423           sw a5,8(sp)
 308: 00e12623           sw a4,12(sp)
 30c: 40002703           lw a4,1024(zero) # 400 <simresult>
 310: 0000f7b7           lui a5,0xf
 314: 11178793           addi a5,a5,273 # f111 <_end+0xece5>
 318: 00f72023           sw a5,0(a4)
 31c: 00c12703           lw a4,12(sp)
 320: 00812783           lw a5,8(sp)
 324: 01010113           addi sp,sp,16
 328: 10000073           eret

The compiler is inserting the correct isr handling code......
But when simulated with the latest ri5cy core I get:
#  - DGB - write 0 into CTRL
#        2465870000 ps: Illegal instruction (core 0) at PC 0x00000328:
#        2469762000 ps: Illegal instruction (core 0) at PC 0x00000328:

I read in the riscv documentation that eret should now probably be an mret.
(At present I am using the embecosm modified toolchain (gcc).)

where can I download the "official" build gcc build tools for the latest ri5cy core (including all of the ri5cy additions like the hardware loop functionality)?

Many thanks in advance
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update to ri5cy core interrupt system and toolchain - by lightning_fingers - 12-27-2018, 09:25 AM

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