Synthesis 8 core pulp for ASIC

[Athena]

Hello !

I want to synthesis the pulp SoC for 65 nm ASIC technology. Given that I have the Synopsys Compiler available is there a guide as to how proper synthesis of the pulp (with 8 RI5CY) cores can be carried out on the such that the hierarchy of the system is properly maintained during optimizations. 

Is there some example script available to direct the Synopsys compiler (or some other compiler) to perform proper synthesis. 
The final goal is to be able to perform power measurements on the synthesised design. Also, is this power analysis possible with the given repository of the pulp project on github?

[kgf]

Hello !

I want to synthesis the pulp SoC for 65 nm ASIC technology. Given that I have the Synopsys Compiler available is there a guide as to how proper synthesis of the pulp (with 8 RI5CY) cores can be carried out on the such that the hierarchy of the system is properly maintained during optimizations. 

Is there some example script available to direct the Synopsys compiler (or some other compiler) to perform proper synthesis. 
The final goal is to be able to perform power measurements on the synthesised design. Also, is this power analysis possible with the given repository of the pulp project on github?

Technically, the PULP source will compile without issues (i.e. the SystemVerilog will not create problems for synthesis). However 'proper synthesis' probably means getting a circuit (for the 65nm technology) that achieves certain performance characteristics (a combination of area, speed, power constraints). While this is not rocket science, it still requires familiarity with the ASIC design process and experience with the technology. For example, there are a number of 'common cells' 

 https://github.com/pulp-platform/common_cells

that have technology independent behavioral descriptions, that need to be mapped to specific implementations in that technology (clock gate cells, sram macros etc). Especially memories are very important to determine the performance of the system, and the availability of these is one of the issues. 

Power measurements are always tricky, especially with modern processes, the capacitive load is often highly dependent on the routing (which is only estimated during synthesis) and the activity depends entirely on the benchmarks running on the system. As the power consumption is directly proportional to the activity (which can differ by orders of magnitude, depending on the application) it is not very easy to get reliable numbers. If possible, I suggest working together with a group that has experience in designing ASICs in the technology mode you are interested in.

We can assure you that the code that is in GitHub is the actual code we use for our tape-outs for multi-core PULP systems, but we can not release technology specific data and related scripts for commercial EDA tools. I think once the open source hardware community expands, these things will also be possible.

[TerryLewis]

Is it possible to generate a netlist using Design Compiler? Is there a sample of something? I'm not a tech guy. Just searching for some tutorials.

[kgf]

Yes, it is possible to generate a netlist (of PULP based systems) using Design Compiler. All ASICs we have made were done this way.

We do not have sample Design Compiler scripts, as this requires technology dependent customizations. What design compiler does is take your HDL description and map it to a set of cells from a target library so that the decsrioption takes physical form. There are some cells (clock gates, I/O cells, memory macros) that need to be specific to the technology. In addition the constraints that you have (clock speed, input output delays etc), need to be adjusted to the technology as well.

I am afraid for this, you will need to have some technical help, it can not be done in a technology agnostic way.

But in principle (ignoring all the technical little details), just analyze everything. elaborate the top file and run compile_ultra, and it will work. There is nothing out of the ordinary needed to get PULP to compile on Design Compiler

I hope that helps