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Hi all,
I guess the current FLL model in PULP setup is not synthesizable. I want to make my own ASIC and looking for open source FLL IPs.
Has anyone used such an IP?
Also wanted to check on my understanding that FLL in its current form is not synthesizable.
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The FLL will need a DCO which has a bit of an analog block inside. That block (unfortunately) we are not allowed to share as it is technology dependent analog IP. Basically an FLL is practical if you are looking for on-chip clocks higher than 200-300 MHz. Otherwise external clocks can easily be pushed through the pads.
Finding a usable / available clocking IP is not very easy, in the end, we were forced to design our own.
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(02-28-2022, 02:37 PM)kgf Wrote: The FLL will need a DCO which has a bit of an analog block inside. That block (unfortunately) we are not allowed to share as it is technology dependent analog IP. Basically an FLL is practical if you are looking for on-chip clocks higher than 200-300 MHz. Otherwise external clocks can easily be pushed through the pads.
Finding a usable / available clocking IP is not very easy, in the end, we were forced to design our own.
Thanks for this insight.
