Synthesis with Intel FPGA Quartus
Did anybody check that the PULP platform (in general, I mean several projects) SystemVerilog compiles with Intel FPGA Quartus toolchain ?

I tried with cvfpu and did not work for me. Maybe I missed something, but I had the impression that you are using some SystemVerilog features not supported by Quartus Prime (v. 21.1).
Can you maybe elaborate? Altera devices are not frequently targeted by us (there is nothing wrong with them, we just ended up using more Xilinx boards for historical reasons), so we might have missed something. But of you can open an issue on GitHub someone might be able to fix it easily. 

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