05-16-2019, 11:24 AM
(05-16-2019, 10:47 AM)fconti Wrote: 1. Might be a recent name change, I saw some merge request with respect to that... will check
2. gf22_fll is just a stub for synthesis in an ASIC technology. For simulation you use a behavioral model ( I believe it’s called generic_fll). For synthesis of any kind you’ll have to provide your own clock generator (FLL or PLL).
2. Yes, that is what is also assumed. This FLL is instantiated for Soc_clk_reset_gen module and not bypassed in synthesis like it is in FPGA.
So I will now make blackbox for that.