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Thread / Author			Replies	Views	Last Post [asc]
		Resource Utilization of PULPino/PULPissimo in FPGA Mwind	4	4,220	01-27-2021, 10:37 PM Last Post: zorrolee777
		Failed at building the RTL simulation platform Jackie Zhang	4	3,413	01-27-2021, 05:00 AM Last Post: Jackie Zhang
		simple runtime vs full SDK, when to use which one? LarsKeuninckx	2	2,521	01-25-2021, 11:00 AM Last Post: LarsKeuninckx
		μClinux on Ibex or CV32E40P? limone	3	3,052	01-22-2021, 04:29 AM Last Post: limone
		power efficient risc-v core limone	0	1,357	01-21-2021, 11:20 PM Last Post: limone
		Maximum frequency obtained when synthesizing the RI5CY core multiplier with 28 FD-SOI Olivier	1	1,572	01-18-2021, 12:57 PM Last Post: kgf
		Help to run Hello Example igor.lima	4	3,390	01-12-2021, 07:00 PM Last Post: igor.lima
		[Vivado] behavioural simulation won't start andrea.spitale	7	6,204	01-08-2021, 01:40 PM Last Post: LarsKeuninckx
		Configuring Pulpissimo as IP for Vivado IP Integrator to use AXI peripherals FrankieTankie	0	1,013	01-07-2021, 03:53 PM Last Post: FrankieTankie
		The signed/unsigned operation support by the Dotp-Unit of the RI5CY core Olivier	1	1,403	01-05-2021, 10:53 AM Last Post: kgf
		Does Pulpissimo already contain VCC & GND pins? traVc	3	2,132	01-03-2021, 10:09 PM Last Post: kgf
		Where is the "get started" documentation? byllgrim	9	15,258	12-29-2020, 06:45 PM Last Post: kgf
		Error while updating IPs LPLA	3	3,521	12-11-2020, 01:59 AM Last Post: LanXu
		How to solve the problem of missing modules “pulpissimo”？ LanXu	1	1,632	12-08-2020, 09:13 AM Last Post: meggiman
		Is there an IDE? nikolas	2	2,143	11-19-2020, 08:49 AM Last Post: nikolas
		PULPissimo FLL bypass Supra	5	3,968	11-06-2020, 09:34 AM Last Post: Supra
		several questions about Pulpissimo SoC platform ninipa	4	5,253	11-05-2020, 07:34 PM Last Post: stefanct
		Building an RTL simulation platform Error RiscV	1	2,003	11-03-2020, 10:27 AM Last Post: kgf
		how to manipulating of GPIOs on Pulpissino platform mapletree	5	8,677	10-18-2020, 03:57 AM Last Post: stefanct
		Pulpissimo- errors during FPGA synthesis. plumerai	2	2,977	10-01-2020, 09:38 AM Last Post: plumerai
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