Moderated By: Moderators, Super Moderators

Mark this forum read PULP General questions
Thread / Author			Replies	Views	Last Post [asc]
		Compiling for RISCY without FP? LarsKeuninckx, 01-27-2021, 10:56 AM	2	8,904	01-28-2021, 09:28 AM Last Post: LarsKeuninckx
		Resource Utilization of PULPino/PULPissimo in FPGA Mwind, 11-20-2020, 08:06 AM	4	16,121	01-27-2021, 10:37 PM Last Post: zorrolee777
		Failed at building the RTL simulation platform Jackie Zhang, 01-25-2021, 11:58 AM	4	14,184	01-27-2021, 05:00 AM Last Post: Jackie Zhang
		simple runtime vs full SDK, when to use which one? LarsKeuninckx, 01-21-2021, 12:37 PM	2	9,803	01-25-2021, 11:00 AM Last Post: LarsKeuninckx
		μClinux on Ibex or CV32E40P? limone, 01-15-2021, 05:13 AM	3	12,839	01-22-2021, 04:29 AM Last Post: limone
		power efficient risc-v core limone, 01-21-2021, 11:20 PM	0	4,449	01-21-2021, 11:20 PM Last Post: limone
		Maximum frequency obtained when synthesizing the RI5CY core multiplier with 28 FD-SOI Olivier, 01-18-2021, 08:57 AM	1	6,399	01-18-2021, 12:57 PM Last Post: kgf
		[Vivado] behavioural simulation won't start andrea.spitale, 12-10-2020, 11:14 AM	7	27,309	01-08-2021, 01:40 PM Last Post: LarsKeuninckx
		Configuring Pulpissimo as IP for Vivado IP Integrator to use AXI peripherals FrankieTankie, 01-07-2021, 03:53 PM	0	4,015	01-07-2021, 03:53 PM Last Post: FrankieTankie
		The signed/unsigned operation support by the Dotp-Unit of the RI5CY core Olivier, 01-05-2021, 09:42 AM	1	6,002	01-05-2021, 10:53 AM Last Post: kgf
		Does Pulpissimo already contain VCC & GND pins? traVc, 01-03-2021, 06:16 PM	3	10,270	01-03-2021, 10:09 PM Last Post: kgf
		Where is the "get started" documentation? byllgrim, 01-14-2019, 10:24 AM	9	37,768	12-29-2020, 06:45 PM Last Post: kgf
		How to solve the problem of missing modules “pulpissimo”？ LanXu, 12-08-2020, 09:05 AM	1	6,764	12-08-2020, 09:13 AM Last Post: meggiman
		Is there an IDE? nikolas, 11-18-2020, 04:04 PM	2	8,685	11-19-2020, 08:49 AM Last Post: nikolas
		several questions about Pulpissimo SoC platform ninipa, 04-07-2020, 03:33 AM	4	15,758	11-05-2020, 07:34 PM Last Post: stefanct
		Building an RTL simulation platform Error RiscV, 11-03-2020, 10:24 AM	1	7,381	11-03-2020, 10:27 AM Last Post: kgf
		Pulpissimo- errors during FPGA synthesis. plumerai, 09-25-2020, 04:23 PM	2	10,293	10-01-2020, 09:38 AM Last Post: plumerai
		Adding custom instructions into RI5CY core plumerai, 09-25-2020, 09:04 AM	4	14,963	09-25-2020, 12:29 PM Last Post: plumerai
		FPGA: Printing UART on minicom possible? LPLA, 09-23-2020, 03:42 PM	0	4,310	09-23-2020, 03:42 PM Last Post: LPLA
		Memset in the disassembly section RiscV, 09-11-2020, 12:09 PM	5	16,388	09-14-2020, 07:02 AM Last Post: RiscV
Sort by: Subject Sort by: Last Post Sort by: Author Sort by: Creation Time Sort by: Replies Sort by: Views Order: Ascending Order: Descending From: Today From: 5 Days Ago From: 10 Days Ago From: 20 Days Ago From: 50 Days Ago From: 75 Days Ago From: 100 Days Ago From: The Last Year From: The Beginning