December 3, 2018
If you were looking for a complete microcontroller development system based on PULP, now you have a new option. Check out the RV32M1VEGA development board by open-isa. VEGABoard is an evaluation board supporting RISC-V cores based RV32M1Wireless Microcontrollers. It integrates a radio tranceiver, ARM Cortex M4 CPU, ARM Cortex M0 CPU and our RI5CY MCU and Zero-Riscy MCU into a single unit. Learn more about VEGABoard's parameters from the documentation.
November 29, 2018
The Princeton Parallel Group led by David Wentzlaff, and the Digital Circuits and Systems Group of ETH Zurich led by Luca Benini have joined forces to bring you the OpenPiton open-source research processor platform with first-class support for 64-bit Ariane RISC-V cores. The latest update of the open-source Ariane processor, (Ariane IV) now supports the P-Mesh cache system from OpenPiton, and with today's OpenPiton release 10, we have our first working system.
November 29, 2018
We are happy to announce Ariane IV. Besides many small performance improvements, bug fixes and enhancements, we now support booting an upstream RISC-V Linux on the Genesys2 FPGA board by Digilent. Check the following link to access pre-built bitfiles and SD images or have a look at the build flow on GitHub.
October 3, 2018
Congratulations to Francesco Conti and Davide Schiavone who won The Best Paper Award at CODES+ISSS 2018, Torino for their paper on XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference. You can find their paper on arXiv.
September 23, 2018
Davide Rossi and Frank Gurkaynak participated at ORConf 2018 in Gdansk, Poland organized by the FOSSi Foundation. Davide presented PULP Project updates, while Frank discussed the challenges of open-source hardware. Frank also represented PULP in the open-source silicon panel. The PULP team enjoyed interesting discussions on open-source topics in a relaxed atmosphere, as well as tasty Polish cuisine.
September 17, 2018
HERO is our open-source, FPGA-based heterogeneous SoC research platform that combines a fully modifiable RISC-V manycore accelerator with an ARM Cortex-A host processor. In addition to a silicon-proven RISC-V manycore accelerator, HERO includes a heterogeneous software stack that supports OpenMP 4.5 and Shared Virtual Memory for transparent accelerator programming; a cycle-accurate, non-interfering event tracing infrastructure complemented by a flexible event analysis and profiling framework and an automated implementation and validation solution that enables efficient research and development on all software and hardware layers. Learn more.
June 11, 2018
Save the Dates! The PULP team will be organizing the next RISC-V workshop. The event will take place at ETH Zurich, Switzerland, 11-13 June 2019. We will let you know more, as soon as we work out the details.
August 8, 2018
We are happy to announce that QuickLogic has started collaboration with ETH Zurich to integrate QuickLogic's ArcticPro embedded FPGA (eFPGA) technology into PULP platform. PULP will develop an SoC integrating RISC-V cores and eFPGA technology, enabling users to offload critical functions from the processors and implement them in eFPGA fabric. The fully integrated system with eFPGA is expected to be available Q1' 2019. Learn more...
July 26, 2018
We would like to introduce to you our new colleague Moritz Schneider who will soon start working on security extensions on PULP systems at IIS ETH Zurich. We hope he will like it with us.
July 17 - 20, 2018
The PULP team participated in The Noise in Physical System Summer School in Perugia devoted to physical foundations and practical applications of energy transformations at micro and nanoscales. Davide, Andrea, Giuseppe, Fabian, Stefan, and Frank from our team also contributed to the great variety of interesting talks. You can find their talks here. Additionally, the PULP team has enjoyed great food, the Umbria jazz festival, as well as the trip to Lake Trasimeno.