Latest news

PULP at HiPEAC Bologna and The European Green Deal

January 24, 2020

The annual HiPEAC conference, Bologna 2020 just successfully concluded and as the venue is the second home of PULP, our team couldn't miss the opportunity to attend and present their work. You can find the presentations of Luca, Davide and Frank here. Additionally, Frank co-organized the Eurolab4HPC Industrial session on Open HW which turned out to be a great success. As part of the conference, the EC's Sandro D'Elia announced trillion-Euro Green Deal to make Europe the world's first climate neutral continent by 2050 and as PULP and energy efficiency go hand in hand, we will do our best to contribute. Read more in EETimes.

PULP inside OpenHW Group's heterogeneous multi-core processor

December 11, 2019

OpenHW Group is going to tape out a heterogeneous multi-core processor based on the NXP iMX platform incorporating open source CORE-V components. The 64-bit CV64A core in the CORE-V Chassis is based on the RV64GC RISC-V core IP, originally developed as part of PULP. Optimized for performance, the CV64A core will be capable of clock frequencies of 1.5GHz. Learn more here.

Google releases OpenTitan

November 5, 2019

Google's OpenTitan, an open source silicon root of trust project, with our Ibex as a key element, has just been announced. Silicon RoT can help ensure that the hardware infrastructure and the software that runs on it remain in their intended, trustworthy state by verifying that the critical system components boot securely using authorized and verifiable code. Several organisations are already participating including ETH Zurich, Google, G+D Mobile Security, Nuvoton, Western Digital and lowRISC. Learn more here and on Google's blog..

Our team released PULP-NN

July 29, 2019

Angelo Garofalo, Manuele Rusci, Francesco Conti and Davide Rossi from our team have released PULP-NN, a multicore computing library to run Quantized Neural Networks on our PULP platform or any of its multi-core (cluster) embodiments and is much like the CMSIS-NN (ARM) data flow and data layout. The first release supports 8-bit weights and activations, and further updates will also include support for sub-byte data operands, down to 1-bit. Learn more here.

RISC-V Workshop and WOSH in Zurich have been a success

June 20, 2019

The RISC-V Workshop and the Week of Open Source hardware at ETH Zurich are now over and we are very proud to have hosted and co-organized this event, an acknowledgement of the growing importance of the RISC-V architecture. During the four days of the workshop and the WOSH tutorials we had the opportunity to learn from top class speakers, meet interesting people, as well as enjoy the views of Zurich. It's been a great pleasure to meet you all. You can find the photos from the event here.

OpenHW Group has been created and PULP is in

June 7, 2019

A new not-for-profit global organization has been founded to boost the adoption of open-source processors by providing a platform for collaboration and offering open-source IP for processor cores. Headed by Founder and CEO, Rick O'Connor, the OpenHW Group has already recruited 13 sponsor organizations, among them Alibaba, Bluespec, CMC Microsystems, Embecosm, ETH Zurich, GreenWaves, Imperas, Metrics, Mythic AI, NXP, Onespin, Silicon Labs and Thales. We are extremely proud to contribute the cores from our PULP Platform into the OpenHW Group family of Core-V cores. Learn more about the OpenHW Group.

lowRISC expands and appoints ETH Zurich to its Board of Directors

May 16, 2019

Prof. Luca Benini (PULP, ETH Zurich) together with Dominic Rizzo and Ron Minnich (Google) have joined the Board of Directors of lowRISC. This is in line with the aim of the organisation to lower the barriers to producing custom silicon, enabling research and FPGA experimentation, and establishing an ecosystem around open silicon designs. PULP is contributing its Zero-riscy processor core which will be further developed under the name 'Ibex'. Read more here.

Zero-riscy now at LowRISC as Ibex

May 7, 2019

Problem finding our Zero-riscy core? It has a new home at LowRISC, which have promised to take good care of it. To mark this change we have renamed the core Ibex (Mountain Goat). The repository with all its comments and change history now resides under and will continue to remain compatible to our project.

PULP has a Youtube channel

April, 2019

You can now watch PULP related projects and news on the Youtube channel that was started by Daniele Palossi from our team. Check out our first videos on the autonomous AI PULP Dro-Net and BioWolf. We would like to thank all the early subscribers - your support made it possible to reach the required mark for our own URL in no time.

PULP and the RISC-V tutorial at HIPEAC19

January 24, 2019

Andreas, Fabian, Michael, Frank and Alex the Bear from the PULP team have participated at HIPEAC19 in Valencia. During the first day of the event, they have given a RISC-V tutorial that included presentations, as well as hands-on related to PULP SDK, the Heteregeneous Research Platform Hero, PowerPULP and OpenPiton+Ariane. You can find the slides here. We would like to thank all the participants that attended the tutorial. The PULP team has also enjoyed the hospitality of the HIPEAC organising team, especially the walking dinner at the City of Arts and Sciences designed by Calatrava.

VEGABoard - New development board with PULP inside

December 3, 2018

If you were looking for a complete microcontroller development system based on PULP, now you have a new option. Check out the RV32M1VEGA development board by open-isa. VEGABoard is an evaluation board supporting RISC-V cores based RV32M1Wireless Microcontrollers. It integrates a radio tranceiver, ARM Cortex M4 CPU, ARM Cortex M0 CPU and our RI5CY MCU and Zero-Riscy MCU into a single unit. Learn more about VEGABoard's parameters from the documentation.

Announcing OpenPiton with Ariane

November 29, 2018

The Princeton Parallel Group led by David Wentzlaff, and the Digital Circuits and Systems Group of ETH Zurich led by Luca Benini have joined forces to bring you the OpenPiton open-source research processor platform with first-class support for 64-bit Ariane RISC-V cores. The latest update of the open-source Ariane processor, (Ariane IV) now supports the P-Mesh cache system from OpenPiton, and with today's OpenPiton release 10, we have our first working system.

The brand new Ariane IV launched

November 29, 2018

We are happy to announce Ariane IV. Besides many small performance improvements, bug fixes and enhancements, we now support booting an upstream RISC-V Linux on the Genesys2 FPGA board by Digilent. Check the following link to access pre-built bitfiles and SD images or have a look at the build flow on GitHub.

Francesco and Davide won The Best Paper Award at CODES+ISSS 2018

October 3, 2018

Congratulations to Francesco Conti and Davide Schiavone who won The Best Paper Award at CODES+ISSS 2018, Torino for their paper on XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference. You can find their paper on arXiv.

PULP participated at ORConf 2018

September 23, 2018

Davide Rossi and Frank Gurkaynak participated at ORConf 2018 in Gdansk, Poland organized by the FOSSi Foundation. Davide presented PULP Project updates, while Frank discussed the challenges of open-source hardware. Frank also represented PULP in the open-source silicon panel. The PULP team enjoyed interesting discussions on open-source topics in a relaxed atmosphere, as well as tasty Polish cuisine.

HERO has been just released

September 17, 2018

HERO is our open-source, FPGA-based heterogeneous SoC research platform that combines a fully modifiable RISC-V manycore accelerator with an ARM Cortex-A host processor. In addition to a silicon-proven RISC-V manycore accelerator, HERO includes a heterogeneous software stack that supports OpenMP 4.5 and Shared Virtual Memory for transparent accelerator programming; a cycle-accurate, non-interfering event tracing infrastructure complemented by a flexible event analysis and profiling framework and an automated implementation and validation solution that enables efficient research and development on all software and hardware layers. Learn more.

Confirmed: RISC-V workshop at ETH Zurich

June 11, 2018

Save the Dates! The PULP team will be organizing the next RISC-V workshop. The event will take place at ETH Zurich, Switzerland, 11-13 June 2019. We will let you know more, as soon as we work out the details.

QuickLogic on board with PULP

August 8, 2018

We are happy to announce that QuickLogic has started collaboration with ETH Zurich to integrate QuickLogic's ArcticPro embedded FPGA (eFPGA) technology into PULP platform. PULP will develop an SoC integrating RISC-V cores and eFPGA technology, enabling users to offload critical functions from the processors and implement them in eFPGA fabric. The fully integrated system with eFPGA is expected to be available Q1' 2019. Learn more...

The PULP team has a new member

July 26, 2018

We would like to introduce to you our new colleague Moritz Schneider who will soon start working on security extensions on PULP systems at IIS ETH Zurich. We hope he will like it with us.

The PULP team attended the NiPS Summer School

July 17 - 20, 2018

The PULP team participated in The Noise in Physical System Summer School in Perugia devoted to physical foundations and practical applications of energy transformations at micro and nanoscales. Davide, Andrea, Giuseppe, Fabian, Stefan, and Frank from our team also contributed to the great variety of interesting talks. You can find their talks here. Additionally, the PULP team has enjoyed great food, the Umbria jazz festival, as well as the trip to Lake Trasimeno.