September 17, 2018
HERO is our open-source, FPGA-based heterogeneous SoC research platform that combines a fully modifiable RISC-V manycore accelerator with an ARM Cortex-A host processor. In addition to a silicon-proven RISC-V manycore accelerator, HERO includes a heterogeneous software stack that supports OpenMP 4.5 and Shared Virtual Memory for transparent accelerator programming; a cycle-accurate, non-interfering event tracing infrastructure complemented by a flexible event analysis and profiling framework and an automated implementation and validation solution that enables efficient research and development on all software and hardware layers. Learn more.
June 11, 2018
Save the Dates! The PULP team will be organizing the next RISC-V workshop. The event will take place at ETH Zurich, Switzerland, 11-13 June 2019. We will let you know more, as soon as we work out the details.
August 8, 2018
We are happy to announce that QuickLogic has started collaboration with ETH Zurich to integrate QuickLogic's ArcticPro embedded FPGA (eFPGA) technology into PULP platform. PULP will develop an SoC integrating RISC-V cores and eFPGA technology, enabling users to offload critical functions from the processors and implement them in eFPGA fabric. The fully integrated system with eFPGA is expected to be available Q1' 2019. Learn more...
July 26, 2018
We would like to introduce to you our new colleague Moritz Schneider who will soon start working on security extensions on PULP systems at IIS ETH Zurich. We hope he will like it with us.
July 17 - 20, 2018
The PULP team participated in The Noise in Physical System Summer School in Perugia devoted to physical foundations and practical applications of energy transformations at micro and nanoscales. Davide, Andrea, Giuseppe, Fabian, Stefan, and Frank from our team also contributed to the great variety of interesting talks. You can find their talks here. Additionally, the PULP team has enjoyed great food, the Umbria jazz festival, as well as the trip to Lake Trasimeno.