PULP Conferences and Workshops

Conference and workshop materials

Cyprus, 2022
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster
Michael P Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank Gurkaynak and Luca Benini

San Francisco, 2022
An FPGA-based Hardware-In-The-Loop co-design for Real-Time Power and Thermal Management emulation
Alessandro Ottaviano, Luca Benini

Samos, 2022
ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Corrado Bonfanti, Simone Benatti, Davide Rossi, Luca Benini, Andrea Bartolini
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-Core MCUs through Performance-Driven Autotuning
Davide Nadalini, Manuele Rusci, Giuseppe Tagliavini, Leonardo Ravaglia, Luca Benini, Francesco Conti

2022, Paris
The RISC-V based Stencil Tensor Accelerator of EPI
Matheus Cavalcante
A RISC-V Heterogeneous SoC for Embedded Devices
Luca Valente, Mattia Sinigaglia, Yvan Tortorella, Davide Rossi and Luca Benini
Agile Design Methodology for Accelerator-Rich Cluster-based RISC-V SoC
Gianluca Bellocchi, Alessandro Capotondi, Luca Benini and Andrea Marongiu
whISPer: Enhancing MemPool to make an Open and General-Purpose Image Signal Processor
Sergio Mazzola, Samuel Riedel, Matheus Cavalcante, and Luca Benini
ControlPULP: A Multi-Core RISC-V Power Controller for HPC Processors
Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Davide Rossi, Luca Benini, Andrea Bartolini
Removing Load-use dependencies bottleneck from CVA6 application class core
Gianmarco Ottavi, Davide Rossi, and Luca Benini

2022 (virtual)
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration
Matheus Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto Garcia-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini
Ternarized TCN for µJ/Inference Gesture Recognition from DVS Event Frames
Georg Rutishauser, Moritz Scherer, Tim Fischer, Luca Benini
SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions
Alfio Di Mauro, Arpan Suravi Prasad, Zhikai Huang, Matteo Spallanzani, Francesco Conti, Luca Benini
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low- Power SoCs
Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti

2021 (online)
Open Source On-Chip Communication from Edge to Cloud: the PULP experience
Davide Rossi
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication
Thomas Benz
HERO: A Heterogenous Research Platform to Explore HW/SW Codesign and RISC-V manycore accelerators
Luca Bertaccini
Manticore as an NoC Case Study: A 4096 Chiplet-based Architecture for Ultra-Efficient Floating-Point Computing
Florian Zaruba

Tricking Dr von Neumann with Magic Birds: from Snitch to Manticore and Occamy
Luca Benini

2021 ACM Europe Summer School
Many Shades of Machine Learning Acceleration - An Open RISC-V Platform Perspective
Luca Benini

ACACES 2021 Fiuggi
Working with RISC-V: from open ISA to open Architecture to open Hardware
Luca Benini, Davide Rossi

2021 (online)
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
A. Garofalo, G. Ottavi, A. Di Mauro, F. Conti, L. Benini, D. Rossi
A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range
Thomas Benz, Luca Bertaccini, Florian Zaruba, Fabian Schuiki,Frank K. Gurkaynak, Luca Benini

Visions of ECS beyond 2030
Open Source HW and RISC-V: Linked, but not the same
Luca Benini

EMEA 2021 (online)
Energy-efficient TCN-Extensions for a TNN accelerator
Tim Fischer
Low-Power License Plate Detection and Recognition on a RISC-V Multi-Core MCU-based Vision System
Lorenzo Lamberti

2021 (online)
Open source HW solutions for EdgeAI: PULP platform in action
Frank Gurkaynak

2021 (online)
How RISC-V can help in security research
Frank Gurkaynak

2021 (online)
Many shades of acceleration - An Open TinyML Platform Perspective
Luca Benini
CUTIE - Beyond PetaOp/s/W Ternary DNN Acceleration
Moritz Scherer

2021 (online)
Seven stories from seven years of PULP project
Luca Benini

2021 (online)
RISC-V for Acceleration of Data-Parallel Workloads
Luca Benini

2021 (virtual)
Moore's Law is In trouble... More Jobs in IC Design!
Luca Benini
In-Sensor Machine Learning Heterogeneous computing in a mW
Luca Benini
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core
Nils Wistoff, Moritz Schneider, Frank Gurkaynak, Luca Benini and Gernot Heiser
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra
Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler and Luca Benini
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect
Matheus Cavalcante, Samuel Riedel, Antonio Pullini and Luca Benini
Funfliber-Drone: A Modular Open-Platform 18-grams Autonomous Nano-Drone
Hanna Mueller, Daniele Palossi, Stefan Mach, Francesco Conti and Luca Benini
Analyzing Memory Interference of FPGA Accelerators on Multicore Hosts in Heterogeneous Reconfigurable SoCs
Maxim Mattheeuws, Bjorn Forsberg, Andreas Kurth and Luca Benini
FlyDVS: An Event-Driven Wireless Ultra-Low Power Visual Sensor Node
Alfio Di Mauro, Moritz Scherer, Jordi Fornt Mas, Basile Bougenot, Michele Magno, Luca Benini
RISC-V for Real-time MCUs - Software Optimization and Microarchitectural Gap Analysis
Robert Balas, Luca Benini

2020 (online)
A Tiny RISC-V Floating-Point Unit
Luca Bertaccini
An Open-Source Flow for DNNs on Ultra-Low-Power RISC-V Cores
Francesco Conti
CORE-V MCU SoC, Open Source, 22nm Embedded MCU with eFPGA
Florian Zaruba
Time Protection: Preventing Microarchitectural Timing Channels on RISC-V
Nils Wistoff

OSD Forum 2020 (online)
Overview of CORE-V CVE4, CVA6 & PULP Development at ETHZ
Davide Schiavone
Overview of CORE-V MCU & APU FPGA based platforms
Florian Zaruba

2020 (online)
Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing
Florian Zaruba, Fabian Schuiki

ACACES 2020 (online)
Working with RISC-V: from open ISA to open Architecture to open Hardware
Luca Benini, Frank Gurkaynak

ICS 2020 (online)
Seven stories from seven years of PULP project
Frank Gurkaynak
RISC-V open-ISA and open-HW - a Swiss army knife for HPC
Andrea Bartolini

Grenoble, 2020 (virtual)
Open, Parallel Ultra-Low Power Platforms for Extreme Edge AI
Luca Benini
TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE
Rohit Prasad, S. Das, K. J. M. Martin, G. Tagliavini, P. Coussy, L. Benini, and D. Rossi
XpulpNN: Accelerating Quantized Neural Networks On RISC-V Processors Through ISA Extensions
Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Davide Rossi, Luca Benini
Compressing Subject-specific Brain-Computer Interface Models into One Model by Superposition in Hyperdimensional Space
Michael Hersche, Philipp Rupp, Luca Benini , Abbas Rahimi

Barcelona, 2020
RISC-V for IoT, the PULP experience
Frank Gurkaynak

Bologna, 2020
Extreme Edge AI on Open Hardware
Luca Benini
Energy efficient computing from Exascale to MicroWatts: The RISC-V playground
Luca Benini
PULP: Open Hardware at the Edge of the IoT
Davide Rossi
Will open source hardware solve your security issues?
Frank K. Gurkaynak

Jeju, 2019
NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22nm FD-SOI
Fabian Schuiki

Bordeaux, 2019
What has PULP been up to lately?
Frank K. Gurkaynak

Perugia, 2019
Energy-Efficient Heterogeneous Design
Luca Benini
PULP: A Multi-Core Platform for Micropower In-Sensor Analytics
Davide Rossi
Understanding performance numbers in Integrated Circuit Design
Frank Gurkaynak

Santa Clara, 2019
The Parallel Ultra Low Power Platform - RISC-V Tutorial at HotChips 2019
Fabian Schuiki

Hype vs Reality - What can RISC-V do for research in safety, reliability and security
Frank Gurkaynak

A PULP Based Wireless Multi-Sensor Platform for Wearable Applications
Manuel Eggimann, Stefan Mach, Michele Magno, Luca Benini

Zurich, 2019
PULP and HERO Tutorial
Andreas Kurth
OpenPiton + Ariane in Action
Princeton University and ETH Zurich
BENDER - A dependency management tool for hardware design projects
Fabian Schuiki
WOSH: Understanding and working with PULP   New
Davide Pasquale Schiavone

Zurich, 2019
Energy efficient computing from Exascale to MicroWatts: The RISC-V playground
Luca Benini
PULP Platform, what's next?
Frank K. Gurkaynak
OpenPiton+Ariane: The First Linux-Booting Open-Source RISC-V Manycore
Jonathan Balkind, Michael Schaffner
PULP-NN: An Open-Source Library for DeeplyEmbedded and Quantized Neural Networks (QNNs) on a RISC-V Based Parallel Ultra Low Power Cluster
Angelo Garofalo, Luca Benini
Kosmodrom: Energy Efficient Ariane Cores with Transprecision FPU in 22nm
Fabian Schuiki, Florian Zaruba, Stefan Mach, Luca Benini
VivoSoC: A RISC-V Based Multi-Functional Platform for Miniaturized Medical Instrumentation
F. Glaser, P. Schonle, T. Burger, N. Brun, J. Bosser, L. Benini, and Q. Huang

Valencia, 2019
RISC-V Tutorial - Introduction
Frank K. Gurkaynak
PULP Software Development Kit and Tools
Andreas Kurth, Germain Haugou
PowerPULP Hands-on Session
Fabian Schuiki
HERO: Heterogeneous Research Platform
Andreas Kurth
OpenPiton + ArianeTutorial
Michael Schaffner, Jonathan Balkind

Santa Clara, 2018
ARA: 64-bit RISC-V Vector Implementation in 22nm FDSOI
Matheus Cavalacante, Fabian Schuiki
AI At The Edge Using PULP + EFPGA
Timothy Saxe, Luca Benini
Ultra Low Power Deep-Learning-powered Autonomous Nano Drones
Daniele Palossi, Luca Benini

Dresden, 2018
Mr.Wolf: a 1 GFLOP/s EnergyProportional Parallel Ultra Low Power SoC for IoT Edge Processing
Antonio Pullini, Davide Rossi, Igor Loi, Alfio Di Mauro, Luca Benini

Gdansk, 2018
PULP Project Update
Davide Rossi
Challenges and Opportunities of Open Source Licenced Hardware
Frank K. G¸urkaynak

Perugia, 2018
Overview of integrated support for Transprecision Computing
Andrea Marongiu, Giuseppe Tagliavini
A tool bag for transprecision computing
Giuseppe Tagliavini, Andrea Marongiu
RISC-V ISA/ Microarchitecture
Frank K. G¸«ärkaynak
Parallel Ultra Low-Power Processing (PULP) Systems
Davide Rossi, Frank K. G¸«ärkaynak
PowerPULP Hands-on Session
Fabian Schuiki, Stefan Mach

Barcelona, 2018
RISC-V Meets 22FDX: an Open Source Ultra-low Power Microcontroller Platform for Advanced FDSOI Techonologies
Pasquale D. Schiavone, Sanjay Charagulla
Ariane: An Open-Source 64-bit RISC-V Application Class Processor and latest Improvements
Florian Zaruba
How PULP-based Platforms are Helping Security Research
Frank K. G¸«ärkaynak

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Francesco Conti, Robert Schilling, Pasquale D. Schiavone, Antonio Pullini, Davide Rossi, Frank K. G¸«ärkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard and Luca Benini

PULP: an Open Hardware Platform, The story so far
Frank Kagan G¸«ärkaynak
Our Programmable Multi-Core Accelerator - HERO
Andreas Kurth
Hardware Acceleration in PULP
Francesco Conti
PULP RISC-V Cores - Ariane, RI5CY and friends
Florian Zaruba

Mountain View, CA 2016
KISS PULPino, Updates on PULPino
Florian Zaruba

Cambridge, MA 2016
DSP ISA Extensions for an Open-Source RISC-V Implementation
Davide Schiavone, Davide Rossi, Michael Gautschi, Eric Flamand, Andreas Traber, Luca Benini

Redwood Shores, CA 2016
PULPino: A small single-core RISC-V SoC
Andreas Traber, Florian Zaruba, Sven Stucki, Antonio Pullini, Germain Haugou, Eric Flamand, Frank K. G¸«ärkaynak, Luca Benini

PULPino: A RISC-V based single-core system
Andreas Traber, Sven Stucki, Florian Zaruba, Michael Gautschi, Antonio Pullini, Igor Loi, Davide Rossi, Germain Haugou, Frank Kagan G¸«ärkaynak, Luca Benini