PULP Conferences and Workshops

Valencia, 2019
RISC-V Tutorial - Introduction
Frank K. Gurkaynak
PULP Software Development Kit and Tools
Andreas Kurth, Germain Haugou
PowerPULP Hands-on Session
Fabian Schuiki
HERO: Heterogeneous Research Platform
Andreas Kurth
OpenPiton + ArianeTutorial
Michael Schaffner, Jonathan Balkind

Santa Clara, 2018
ARA: 64-bit RISC-V Vector Implementation in 22nm FDSOI
Matheus Cavalacante, Fabian Schuiki
AI At The Edge Using PULP + EFPGA
Timothy Saxe, Luca Benini
Ultra Low Power Deep-Learning-powered Autonomous Nano Drones
Daniele Palossi, Luca Benini

Dresden, 2018
Mr.Wolf: a 1 GFLOP/s EnergyProportional Parallel Ultra Low Power SoC for IoT Edge Processing
Antonio Pullini, Davide Rossi, Igor Loi, Alfio Di Mauro, Luca Benini

Gdansk, 2018
PULP Project Update
Davide Rossi
Challenges and Opportunities of Open Source Licenced Hardware
Frank K. G¸«ärkaynak

Perugia, 2018
Overview of integrated support for Transprecision Computing
Andrea Marongiu, Giuseppe Tagliavini
A tool bag for transprecision computing
Giuseppe Tagliavini, Andrea Marongiu
RISC-V ISA/ Microarchitecture
Frank K. G¸«ärkaynak
Parallel Ultra Low-Power Processing (PULP) Systems
Davide Rossi, Frank K. G¸«ärkaynak
PowerPULP Hands-on Session
Fabian Schuiki, Stefan Mach

Barcelona, 2018
RISC-V Meets 22FDX: an Open Source Ultra-low Power Microcontroller Platform for Advanced FDSOI Techonologies
Pasquale D. Schiavone, Sanjay Charagulla
Ariane: An Open-Source 64-bit RISC-V Application Class Processor and latest Improvements
Florian Zaruba
How PULP-based Platforms are Helping Security Research
Frank K. G¸«ärkaynak

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Francesco Conti, Robert Schilling, Pasquale D. Schiavone, Antonio Pullini, Davide Rossi, Frank K. G¸«ärkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard and Luca Benini

PULP: an Open Hardware Platform, The story so far
Frank Kagan G¸«ärkaynak
Our Programmable Multi-Core Accelerator - HERO
Andreas Kurth
Hardware Acceleration in PULP
Francesco Conti
PULP RISC-V Cores - Ariane, RI5CY and friends
Florian Zaruba

Mountain View, CA 2016
KISS PULPino, Updates on PULPino
Florian Zaruba

Cambridge, MA 2016
DSP ISA Extensions for an Open-Source RISC-V Implementation
Davide Schiavone, Davide Rossi, Michael Gautschi, Eric Flamand, Andreas Traber, Luca Benini

Redwood Shores, CA 2016
PULPino: A small single-core RISC-V SoC
Andreas Traber, Florian Zaruba, Sven Stucki, Antonio Pullini, Germain Haugou, Eric Flamand, Frank K. G¸«ärkaynak, Luca Benini

PULPino: A RISC-V based single-core system
Andreas Traber, Sven Stucki, Florian Zaruba, Michael Gautschi, Antonio Pullini, Igor Loi, Davide Rossi, Germain Haugou, Frank Kagan G¸«ärkaynak, Luca Benini