Conference and workshop materials
 2024 |
Energy-Efficient Gen AI on Open-Source RISC-V Heterogenous SoCs Victor Jung |
 2024 |
Toward End-to-End Open Platforms for the Embodied AI Era Luca Benini |
 Milan 2024 |
Designing "Artificial Brains" for Next-Generation Autonomous Systems Luca Benini Extending RISC-V for Efficient Overflow Recovery in Mixed-Precision Computations Luca Bertaccini HeroSDK: Streamlining Heterogeneous RISC-V Accelerated Computing From Embedded To High-Performance Systems Cyril Koenig vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems Enrico Zelioli |
 Zurich 2024 |
Toward Gen.AI Pervasive Intelligent Systems: An Open RISC-V platform Approach Luca Benini |
 Berkeley 2024 |
Designing Real SoCs using open EDA tools Luca Benini |
 Sydney 2024 |
Hardware Support for Time Protection Nils Wistoff |
 Raleigh 2024 |
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models On Heterogeneous Microcontrollers Moritz Scherer |
 Turin 2024 |
fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning Nils Wistoff |
 Canary Isles 2024 |
Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC Michael Rogenmoser |
 Bruges 2024 |
Circuits and Systems for Embodied AI Luca Benini Are open source digital design flows ready for mainstream? Frank Gurkaynak |
 Graz 2024 |
Ara: A RISC-V Vector Co-Processor for CVA6 Luca Bertaccini |
 Seattle 2024 |
Multi-resolution Rescored ByteTrack for Video Object Detection on Ultra-low-power Embedded Systems Luca Bompani |
 Hong Kong 2024 |
Spatzformer: Reconfigurable Dual-Core RVV Cluster for Mixed Scalar-Vector Workloads Matteo Perotti |
 Taiwan 2024 |
Designing Linux-capable systems using open EDA tools Philippe Sauter |
 Naples 2024 |
BatDeck: Advancing Nano-drone Navigation with Low-power Ultrasound-based Obstacle Avoidance Hanna Muller |
 San Francisco 2024 |
SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers Paul Scheffler |
 Munich 2024 |
Security and safety using open-source hardware,The story so far. Frank Gurkaynak |
 Munich 2024 |
Industry Academia Collaborations on Open-Source Hardware Frank Gurkaynak SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications Michael Rogenmoser How to tape-out a 64-core RISC-V SoC in under 60 days Frank Gurkaynak and the PULP team Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC Philippe Sauter, Thomas Benz ISA Support for Hardware Resource Partitioning in RISC-V Nils Wistoff DUTCTL: A Flexible Open-Source Framework for Rapid Bring-Up, Characterization, and Remote Operation of Custom-Silicon RISC-V SoCs Thomas Benz |
 Cambridge MA 2024 |
From an Open-Source ISA to Open-Source HW to Open-Source Silicon Luca Bertaccini |
 Yokohama 2024 |
Robust and Efficient Depth-based Obstacle Avoidance for Autonomous Miniaturized UAVs Hanna Muller Fully Onboard Low-Power Localization with Semantic Sensor Fusion on a Nano-UAV using Floor Plans Nicky Zimmerman, Hanna Muller |
 Abu Dhabi 2024 |
Driving Towards Safety: Online PPG-based Drowsiness Detection with TCNs Pierangelo Maria Rapa On-Device Domain Learning for Keyword Spotting on Low-Power Extreme Edge Embedded Systems Cristian Cioflan |
 Zurich 2024 |
Near-Sensor Analytics and Machine Learning for Long-Term Wearable Biomedical Systems Xiaying Wang Wearables and at-body AI for next generation human-machine interfaces: an arm-centric approach Giusy Spacone |
 Greater Noida 2024 |
Open Platforms for the Embodied AI era Luca Benini |
 Valencia 2024 |
MX: Ultra-Low Overhead, Energy-Efficient Matrix Multiplication on RISC-V Vector ISA Matteo Perotti Work In Progress: Linear Transformers for TinyML Moritz Scherer, Cristian Cioflan PELS: A Lightweight and Flexible Peripheral Event Linking System for ULP IoT Processors Alessandro Ottaviano Optimizing Offload Performance in Heterogeneous MPSoCs Luca Colagrande LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation Samuel Riedel Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV Chi Zhang Designing and Scaling Versatile Manycore Systems Samuel Riedel ET02 Tutorial On-Device Continual Learning Meets Ultra-Low Power Processing Manuele Rusci, Davide Nadalini, Cristian Cioflan |
 Kolkata 2024 |
Open Platforms for the Embodied AI era Luca Benini |
 Lugano 2023 |
10 Years of PULP PULP team |
 Istanbul 2023 |
From Nano-Drones to Cars - A RISC-V Open Platform for Next-Generation Autonomous Vehicles Luca Benini Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm Michael Rogenmoser MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS Samuel Riedel, presented by Michael Rogenmoser Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms Ahmad Mirsalari Multi-sensory Anti-collision Design for Autonomous Nano-swarm Exploration Mahyar Pourjabar |
 Lausanne 2023 |
Parallel Ultra-Low Power (PULP) Processing for Next-Generation Wearable EEG Monitoring Luca Benini |
 Lausanne 2023 |
The "Inevitable" Open Platform for Energy-Efficient, High-performance Computing Luca Benini |
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Hamburg 2023 |
WIP: Automatic DNN Deployment on Heterogeneous Platforms: the GAP9 Case Study Luka Macan |
 Sardinia 2023 |
Many Shades of TinyML Acceleration: a RISC-V open platform approach Luca Benini Land & Localize: An Infrastructure-free and Scalable Nano-Drones Swarm with UWB-based Localization Mahyar Pourjabar Exploiting Hybrid Modular Redundancy in RISC-V Based Multicore Clusters for Space Computing Yvan Tortorella TransLib: A Library To Explore Transprecision Floating-Point Arithmetic On Multi-Core IoT End-Nodes Ahmad Mirsalari Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays Mattia Sinigaglia Nano Drones: An OpenTitan-based SoC Design for Autonomous Flight and Cyber Security Supporting Visual Communication Maicol Ciani End-to-End DNN Inference on a Massively Parallel Analog In-Memory Computing Architecture Nazareno Bruschi |
 Munich 2023 |
Ten years of PULP: The Evolution of the Species from IoT to HPC Davide Rossi |
 Lisbon 2023 |
Siracusa - Towards On-Sensor Computing for Extended Reality Applications Moritz Scherer |
 Stanford 2023 |
Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs Luca Valente |
 Paris 2023 |
Industry-Grade SystemVerilog IPs And The Open Flow: How We Synthesized Iguana Thomas Benz |
 Samos 2023 |
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster Marco Bertuletti |
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San Francisco 2023 |
Specialisation meets Flexibility: A Heterogeneous Architecture for High-Efficiency, High-Flexibility AR/VR Processing Arpan Prasad |
 Amsterdam 2023 |
On-Device Learning (ODL) on RISC-V Multicore MCUs Davide Nadalini Single-Shot Visual Object Detectors on Nano-Drones Luca Bompani |
 San Francisco 2023 |
Carfield: An Open-Research Platform for Safety, Resilient and Predictable Systems Angelo Garofalo Protego: A Low-Overhead Open-Source I/O Physical Memory Protection Unit for RISC-V Nils Wistoff |
 Iguazu 2023 |
A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks Alessandro Nadalini |
 2023 (online) |
STATIC ANALYSIS OF NON-FUNCTIONAL REQUIREMENTS Energy efficiency Sergio Mazzola |
 Cyprus 2023 |
Land & Localize: An Infrastructure-free and Scalable Nano-Drones Swarm with UWB-based Localization Mahyar Pourjabar |
 2023 (online) |
PULP within the Open Source Hardware Landscape Frank Gurkaynak |
 Hangzhou 2023 |
Free Bits: Latency Optimization of Mixed-Precision Quantized Neural Networks on the Edge Georg Rutishauser |
 Barcelona 2023 |
Open RISC-V Platforms for Energy-Efficient Scalable Computing Luca Benini 10 years of making PULP chips Frank Gurkaynak Towards Full Time Protection of an Open-Source, Out-of-Order RISC-V Core Nils Wistoff Accelerating Irregular Workloads with Cooperating Indexed Stream Registers Paul Scheffler Iguana: An End-to-End Open-Source Linux-capable RISC-V SoC in 130nm CMOS Thomas Benz Parallel Sparse Deep Learning Operators on Lightweight RISC-V Processors Marco Bertuletti |
 Monopoli 2023 |
From Nano-Drones to Cars Luca Benini A Fast and Accurate Optical Flow Camera for Resource-Constrained Edge Applications Jonas Kuhne |
 Monterey, CA 2023 |
ColibriES: End-to-End Efficiency for Neuromorphic Processing at the Edge Georg Rutishauser Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays Mattia Sinigaglia Nano Drones: An OpenTitan-based SoC Design for Autonomous Flight and Cyber Security Supporting Visual Communication Maicol Ciani |
 Hamburg 2023 |
Paving the Road for RISC-V Supercomputers with Open Hardware Luca Benini |
 Venice 2023 |
The first 10 years of PULP Platform and open source HW Frank Gurkaynak Practical Implementations & Cooperation for Reliable Architectures Using Open-Source Hardware Michael Rogenmoser Redundancy Schemes for PULP Systems Yvan Tortorella |
 2023 Antwerp |
PULP: 10 Years of Open Source Hardware Frank Gurkaynak Bio-inspired Autonomous Exploration Policies with CNN-based Object Detection on Nano-drones Lorenzo Lamberti Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor Marco Bertuletti MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster Samuel Riedel TransLib: A Library To Explore Transprecision Floating-Point Arithmetic On Multi-Core IoT End-Nodes Ahmad Mirsalari AXI-PACK: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads Chi Zhang Fully On-board Low-Power Localization with Multizone Time-of-Flight Sensors on Nano-UAVs Hanna Muller End-to-End DNN Inference on a Massively Parallel Analog In-Memory Computing Architecture Nazareno Bruschi Occamy: A 432-core RISC-V Based 2.5D Chiplet System for Ultra-Efficient (Mini-)Floating-Point Computation Gianna Paulin HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC Luca Valente |
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Zurich 2023 |
MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster Samuel Riedel |
 San Francisco 2023 |
A 12.4 TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing
Francesco Conti Is an AI Accelerator All You Need? Overcoming Amdahl's Law With Tightly-Coupled Specialized Accelerators Angelo Garofalo |
 Apropos Winter School, Zurich 2023 |
Low Power Multicore Solutions for Approximation
Luca Benini Transprecision Floating-Point Units Luca Bertaccini |
 San Jose 2022 |
MiniFloat-NN: A RISC-V ISA Extension for Low-Precision NN Training Luca Bertaccini |
 Dallas 2022 |
Open Platforms for Energy-Efficient Scalable Computing Luca Benini |
 Istanbul 2022 |
10 years of Making open source RISC-V based computing architectures Frank Gurkaynak |
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Munich 2022 |
fence.t: hardware support for preventing microarchitectural timing channels Nils Wistoff |
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Cyprus 2022 |
Continual On-device Learning on Multi- Core RISC-V MicroControllers Manuele Rusci |
 San Diego 2022 |
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters Matheus Cavalcante, Domenic Wuethrich, Matteo Perotti, Samuel Riedel, Luca Benini |
 Milan 2022 |
DARKSIDE: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training A. Garofalo, M. Perotti, L. Valente, Y. Tortorella, A. Nadalini, L. Benini, D. Rossi and F. Conti |
 ARITH 2022 (online) |
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores Luca Bertaccini, Gianna Paulin, Tim Fischer, Stefan Mach, Luca Benini |
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2022 (online) |
Kraken: A Direct Event/Frame-Based Multi-sensor Fusion
SoC for Ultra-Efficient Visual Processing in Nano-UAVs Alfio Di Mauro, Moritz Scherer, Davide Rossi, Luca Benini |
 Cyprus 2022 |
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster
Michael P Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank Gurkaynak and Luca Benini |
 San Francisco 2022 |
Soft Tiles: Capturing Physical Implementation Flexibility for
Tightly-Coupled Parallel Processing Clusters Gianna Paulin, Matheus Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank Gurkaynak, Luca Benini An FPGA-based Hardware-In-The-Loop co-design for Real-Time Power and Thermal Management emulation Alessandro Ottaviano, Luca Benini |
 Samos 2022 |
ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Corrado Bonfanti, Simone Benatti, Davide Rossi, Luca Benini, Andrea Bartolini PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-Core MCUs through Performance-Driven Autotuning Davide Nadalini, Manuele Rusci, Giuseppe Tagliavini, Leonardo Ravaglia, Luca Benini, Francesco Conti |
 OSCAR 2022 (ISCA) |
Efficient Systolic Execution on a Shared-Memory
Manycore System
Samuel Riedel, Matheus Cavalcante, Sergio Mazzola, Luca Benini |
 Budapest 2022 |
ControlPULP - Intro: A Scalable RISC-V Power Controller Platform for HPC Processors Andrea Bartolini, Giovanni Bambini Leveraging the PULP Platform to Build Reliable Systems Luca Bertaccini, Michael Rogenmoser |
 Paris 2022 |
The RISC-V based Stencil Tensor Accelerator of EPI Matheus Cavalcante A RISC-V Heterogeneous SoC for Embedded Devices Luca Valente, Mattia Sinigaglia, Yvan Tortorella, Davide Rossi and Luca Benini Agile Design Methodology for Accelerator-Rich Cluster-based RISC-V SoC Gianluca Bellocchi, Alessandro Capotondi, Luca Benini and Andrea Marongiu whISPer: Enhancing MemPool to make an Open and General-Purpose Image Signal Processor Sergio Mazzola, Samuel Riedel, Matheus Cavalcante, and Luca Benini ControlPULP: A Multi-Core RISC-V Power Controller for HPC Processors Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Davide Rossi, Luca Benini, Andrea Bartolini Removing Load-use dependencies bottleneck from CVA6 application class core Gianmarco Ottavi, Davide Rossi, and Luca Benini |
 2022 (virtual) |
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration Matheus Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto Garcia-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini Ternarized TCN for µJ/Inference Gesture Recognition from DVS Event Frames Georg Rutishauser, Moritz Scherer, Tim Fischer, Luca Benini SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions Alfio Di Mauro, Arpan Suravi Prasad, Zhikai Huang, Matteo Spallanzani, Francesco Conti, Luca Benini RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low- Power SoCs Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti |
 2021 (online) |
Open Source On-Chip Communication from Edge to Cloud: the PULP experience Davide Rossi An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication Thomas Benz HERO: A Heterogenous Research Platform to Explore HW/SW Codesign and RISC-V manycore accelerators Luca Bertaccini Manticore as an NoC Case Study: A 4096 Chiplet-based Architecture for Ultra-Efficient Floating-Point Computing Florian Zaruba |
 2021 |
Tricking Dr von Neumann with Magic Birds: from Snitch to Manticore and Occamy Luca Benini |
 2021 ACM Europe Summer School |
Many Shades of Machine Learning Acceleration - An Open RISC-V Platform Perspective Luca Benini |
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ACACES 2021 Fiuggi |
Working with RISC-V: from open ISA to open Architecture to open Hardware Luca Benini, Davide Rossi |
 2021 (online) |
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode A. Garofalo, G. Ottavi, A. Di Mauro, F. Conti, L. Benini, D. Rossi A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range Thomas Benz, Luca Bertaccini, Florian Zaruba, Fabian Schuiki,Frank K. Gurkaynak, Luca Benini |
 Visions of ECS beyond 2030 |
Open Source HW and RISC-V: Linked, but not the same Luca Benini |
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EMEA 2021 (online) |
Energy-efficient TCN-Extensions for a TNN accelerator Tim Fischer Low-Power License Plate Detection and Recognition on a RISC-V Multi-Core MCU-based Vision System Lorenzo Lamberti |
 2021 (online) |
Open source HW solutions for EdgeAI: PULP platform in action Frank Gurkaynak |
 2021 (online) |
How RISC-V can help in security research Frank Gurkaynak |
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2021 (online) |
Many shades of acceleration - An Open TinyML Platform Perspective Luca Benini CUTIE - Beyond PetaOp/s/W Ternary DNN Acceleration Moritz Scherer |
 2021 (online) |
Seven stories from seven years of PULP project Luca Benini |
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2021 (online) |
RISC-V for Acceleration of Data-Parallel Workloads Luca Benini |
 2021 (virtual) |
Moore's Law is In trouble... More Jobs in IC Design! Luca Benini In-Sensor Machine Learning Heterogeneous computing in a mW Luca Benini Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core Nils Wistoff, Moritz Schneider, Frank Gurkaynak, Luca Benini and Gernot Heiser Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler and Luca Benini MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect Matheus Cavalcante, Samuel Riedel, Antonio Pullini and Luca Benini Funfliber-Drone: A Modular Open-Platform 18-grams Autonomous Nano-Drone Hanna Mueller, Daniele Palossi, Stefan Mach, Francesco Conti and Luca Benini Analyzing Memory Interference of FPGA Accelerators on Multicore Hosts in Heterogeneous Reconfigurable SoCs Maxim Mattheeuws, Bjorn Forsberg, Andreas Kurth and Luca Benini FlyDVS: An Event-Driven Wireless Ultra-Low Power Visual Sensor Node Alfio Di Mauro, Moritz Scherer, Jordi Fornt Mas, Basile Bougenot, Michele Magno, Luca Benini RISC-V for Real-time MCUs - Software Optimization and Microarchitectural Gap Analysis Robert Balas, Luca Benini |
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2020 (online) |
A Tiny RISC-V Floating-Point Unit Luca Bertaccini An Open-Source Flow for DNNs on Ultra-Low-Power RISC-V Cores Francesco Conti CORE-V MCU SoC, Open Source, 22nm Embedded MCU with eFPGA Florian Zaruba Time Protection: Preventing Microarchitectural Timing Channels on RISC-V Nils Wistoff |
 OSD Forum 2020 (online) |
Overview of CORE-V CVE4, CVA6 & PULP Development at ETHZ Davide Schiavone Overview of CORE-V MCU & APU FPGA based platforms Florian Zaruba |
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2020 (online) |
Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing Florian Zaruba, Fabian Schuiki |
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ACACES 2020 (online) |
Working with RISC-V: from open ISA to open Architecture to open Hardware Luca Benini, Frank Gurkaynak |
 ICS 2020 (online) |
Seven stories from seven years of PULP project Frank Gurkaynak RISC-V open-ISA and open-HW - a Swiss army knife for HPC Andrea Bartolini |
 Grenoble, 2020 (virtual) |
Open, Parallel Ultra-Low Power Platforms for Extreme Edge AI Luca Benini TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE Rohit Prasad, S. Das, K. J. M. Martin, G. Tagliavini, P. Coussy, L. Benini, and D. Rossi XpulpNN: Accelerating Quantized Neural Networks On RISC-V Processors Through ISA Extensions Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti, Davide Rossi, Luca Benini Compressing Subject-specific Brain-Computer Interface Models into One Model by Superposition in Hyperdimensional Space Michael Hersche, Philipp Rupp, Luca Benini , Abbas Rahimi |
 Barcelona, 2020 |
RISC-V for IoT, the PULP experience Frank Gurkaynak |
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Bologna, 2020 |
Extreme Edge AI on Open Hardware Luca Benini Energy efficient computing from Exascale to MicroWatts: The RISC-V playground Luca Benini PULP: Open Hardware at the Edge of the IoT Davide Rossi Will open source hardware solve your security issues? Frank K. Gurkaynak |
 Jeju, 2019 |
NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22nm FD-SOI Fabian Schuiki |
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Bordeaux, 2019 |
What has PULP been up to lately? Frank K. Gurkaynak |
 Perugia, 2019 |
Energy-Efficient Heterogeneous Design Luca Benini PULP: A Multi-Core Platform for Micropower In-Sensor Analytics Davide Rossi Understanding performance numbers in Integrated Circuit Design Frank Gurkaynak |
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Santa Clara, 2019 |
The Parallel Ultra Low Power Platform - RISC-V Tutorial at HotChips 2019 Fabian Schuiki |
 Stuttgart |
Hype vs Reality - What can RISC-V do for research in safety, reliability and security Frank Gurkaynak |
 Otranto |
A PULP Based Wireless Multi-Sensor Platform for Wearable Applications Manuel Eggimann, Stefan Mach, Michele Magno, Luca Benini |
 Zurich, 2019 |
PULP and HERO Tutorial Andreas Kurth OpenPiton + Ariane in Action Princeton University and ETH Zurich BENDER - A dependency management tool for hardware design projects Fabian Schuiki WOSH: Understanding and working with PULP New Davide Pasquale Schiavone |
 Zurich, 2019 |
Energy efficient computing from Exascale to MicroWatts: The RISC-V playground Luca Benini PULP Platform, what's next? Frank K. Gurkaynak OpenPiton+Ariane: The First Linux-Booting Open-Source RISC-V Manycore Jonathan Balkind, Michael Schaffner PULP-NN: An Open-Source Library for DeeplyEmbedded and Quantized Neural Networks (QNNs) on a RISC-V Based Parallel Ultra Low Power Cluster Angelo Garofalo, Luca Benini Kosmodrom: Energy Efficient Ariane Cores with Transprecision FPU in 22nm Fabian Schuiki, Florian Zaruba, Stefan Mach, Luca Benini VivoSoC: A RISC-V Based Multi-Functional Platform for Miniaturized Medical Instrumentation F. Glaser, P. Schonle, T. Burger, N. Brun, J. Bosser, L. Benini, and Q. Huang |
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Valencia, 2019 |
RISC-V Tutorial - Introduction Frank K. Gurkaynak PULP Software Development Kit and Tools Andreas Kurth, Germain Haugou PowerPULP Hands-on Session Fabian Schuiki HERO: Heterogeneous Research Platform Andreas Kurth OpenPiton + ArianeTutorial Michael Schaffner, Jonathan Balkind |
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Santa Clara, 2018 |
ARA: 64-bit RISC-V Vector Implementation in 22nm FDSOI Matheus Cavalacante, Fabian Schuiki AI At The Edge Using PULP + EFPGA Timothy Saxe, Luca Benini |
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Ultra Low Power Deep-Learning-powered Autonomous Nano Drones Daniele Palossi, Luca Benini |
 Dresden, 2018 |
Mr.Wolf: a 1 GFLOP/s EnergyProportional Parallel Ultra Low Power SoC for IoT Edge Processing Antonio Pullini, Davide Rossi, Igor Loi, Alfio Di Mauro, Luca Benini |
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Gdansk, 2018 |
PULP Project Update Davide Rossi Challenges and Opportunities of Open Source Licenced Hardware Frank K. G urkaynak |
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Perugia, 2018 |
Overview of integrated support for Transprecision Computing Andrea Marongiu, Giuseppe Tagliavini A tool bag for transprecision computing Giuseppe Tagliavini, Andrea Marongiu RISC-V ISA/ Microarchitecture Frank K. G rkaynak Parallel Ultra Low-Power Processing (PULP) Systems Davide Rossi, Frank K. G rkaynak PowerPULP Hands-on Session Fabian Schuiki, Stefan Mach |
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Barcelona, 2018 |
RISC-V Meets 22FDX: an Open Source Ultra-low Power Microcontroller Platform for Advanced FDSOI Techonologies Pasquale D. Schiavone, Sanjay Charagulla Ariane: An Open-Source 64-bit RISC-V Application Class Processor and latest Improvements Florian Zaruba How PULP-based Platforms are Helping Security Research Frank K. G rkaynak |
 Florence |
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics Francesco Conti, Robert Schilling, Pasquale D. Schiavone, Antonio Pullini, Davide Rossi, Frank K. G rkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard and Luca Benini |
 Vienna |
PULP: an Open Hardware Platform, The story so far Frank Kagan G rkaynak Our Programmable Multi-Core Accelerator - HERO Andreas Kurth Hardware Acceleration in PULP Francesco Conti PULP RISC-V Cores - Ariane, RI5CY and friends Florian Zaruba |
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Mountain View, CA 2016 |
KISS PULPino, Updates on PULPino Florian Zaruba |
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Cambridge, MA 2016 |
DSP ISA Extensions for an Open-Source RISC-V Implementation Davide Schiavone, Davide Rossi, Michael Gautschi, Eric Flamand, Andreas Traber, Luca Benini |
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Redwood Shores, CA 2016 |
PULPino: A small single-core RISC-V SoC Andreas Traber, Florian Zaruba, Sven Stucki, Antonio Pullini, Germain Haugou, Eric Flamand, Frank K. G rkaynak, Luca Benini |
 Geneva |
PULPino: A RISC-V based single-core system Andreas Traber, Sven Stucki, Florian Zaruba, Michael Gautschi, Antonio Pullini, Igor Loi, Davide Rossi, Germain Haugou, Frank Kagan G rkaynak, Luca Benini |