PULP Community

Threads

1. power efficient risc-v core (0 Replies)
2. Maximum frequency obtained when synthesizing the RI5CY core multiplier with 28 FD-SOI (1 Reply)
3. Help to run Hello Example (4 Replies)
4. [Vivado] behavioural simulation won't start (7 Replies)
5. Configuring Pulpissimo as IP for Vivado IP Integrator to use AXI peripherals (0 Replies)
6. The signed/unsigned operation support by the Dotp-Unit of the RI5CY core (1 Reply)
7. Does Pulpissimo already contain VCC & GND pins? (3 Replies)
8. Where is the "get started" documentation? (9 Replies)
9. Error while updating IPs (3 Replies)
10. How to solve the problem of missing modules “pulpissimo”？ (1 Reply)
11. Is there an IDE? (2 Replies)
12. several questions about Pulpissimo SoC platform (4 Replies)
13. Building an RTL simulation platform Error (1 Reply)
14. how to manipulating of GPIOs on Pulpissino platform (5 Replies)
15. Pulpissimo- errors during FPGA synthesis. (2 Replies)
16. Adding custom instructions into RI5CY core (4 Replies)
17. FPGA: Printing UART on minicom possible? (0 Replies)
18. Memset in the disassembly section (5 Replies)
19. Error while building SDK (4 Replies)
20. [Pulpissimo]where are the <board_target>.sh ? (8 Replies)