PULP General questions
Threads
- power efficient risc-v core (0 Replies)
- Maximum frequency obtained when synthesizing the RI5CY core multiplier with 28 FD-SOI (1 Reply)
- Help to run Hello Example (4 Replies)
- [Vivado] behavioural simulation won't start (7 Replies)
- Configuring Pulpissimo as IP for Vivado IP Integrator to use AXI peripherals (0 Replies)
- The signed/unsigned operation support by the Dotp-Unit of the RI5CY core (1 Reply)
- Does Pulpissimo already contain VCC & GND pins? (3 Replies)
- Where is the "get started" documentation? (9 Replies)
- Error while updating IPs (3 Replies)
- How to solve the problem of missing modules “pulpissimo”? (1 Reply)
- Is there an IDE? (2 Replies)
- several questions about Pulpissimo SoC platform (4 Replies)
- Building an RTL simulation platform Error (1 Reply)
- how to manipulating of GPIOs on Pulpissino platform (5 Replies)
- Pulpissimo- errors during FPGA synthesis. (2 Replies)
- Adding custom instructions into RI5CY core (4 Replies)
- FPGA: Printing UART on minicom possible? (0 Replies)
- Memset in the disassembly section (5 Replies)
- Error while building SDK (4 Replies)
- [Pulpissimo]where are the <board_target>.sh ? (8 Replies)