PULP Community

Threads

1. Resource Utilization of PULPino/PULPissimo in FPGA (4 Replies)
2. Failed at building the RTL simulation platform (4 Replies)
3. simple runtime vs full SDK, when to use which one? (2 Replies)
4. μClinux on Ibex or CV32E40P? (3 Replies)
5. power efficient risc-v core (0 Replies)
6. Maximum frequency obtained when synthesizing the RI5CY core multiplier with 28 FD-SOI (1 Reply)
7. [Vivado] behavioural simulation won't start (7 Replies)
8. Configuring Pulpissimo as IP for Vivado IP Integrator to use AXI peripherals (0 Replies)
9. The signed/unsigned operation support by the Dotp-Unit of the RI5CY core (1 Reply)
10. Does Pulpissimo already contain VCC & GND pins? (3 Replies)
11. Where is the "get started" documentation? (9 Replies)
12. How to solve the problem of missing modules “pulpissimo”？ (1 Reply)
13. Is there an IDE? (2 Replies)
14. several questions about Pulpissimo SoC platform (4 Replies)
15. Building an RTL simulation platform Error (1 Reply)
16. Pulpissimo- errors during FPGA synthesis. (2 Replies)
17. Adding custom instructions into RI5CY core (4 Replies)
18. FPGA: Printing UART on minicom possible? (0 Replies)
19. Memset in the disassembly section (5 Replies)
20. Error while building SDK (4 Replies)