PULP Community

Threads

1. File reading from host example (0 Replies)
2. Pulpissimo bitstream generation. (12 Replies)
3. Error on Macro 'DMI_JTAG_IDCODE is not defined when built pulp RTL simulation pfm (0 Replies)
4. Integrating NVDLA with PULPissimo (0 Replies)
5. which spike version for ri5cy? (0 Replies)
6. xilinx memories in pulpissimo L2 (1 Reply)
7. Porting Ariane to KC705 (1 Reply)
8. FPGA build (2 Replies)
9. how to add a new ISR into interrupt vector table (0 Replies)
10. Using HAL headers in HERO project (0 Replies)
11. hero-sdk for ZynqMP (7 Replies)
12. How to simulate the bootloader with flash S25fs256s verilog model for pulpino? (0 Replies)
13. Pulpissimo synthesis error (0 Replies)
14. Lower number of cores on HERO (3 Replies)
15. Pulpissimo Synthesis content (3 Replies)
16. How to do post-synthesis simulation of PULPino after generating netlist using DC (2 Replies)
17. [HERO] Userland application debugging (1 Reply)
18. [PULP] Peripheral bus memory map (1 Reply)
19. clock problem when writing sdc file in order to synthesize PULPino (2 Replies)
20. Pulpissimo synthesis (5 Replies)