PULP Community

Threads

1. FPGA build (2 Replies)
2. how to add a new ISR into interrupt vector table (0 Replies)
3. Using HAL headers in HERO project (0 Replies)
4. hero-sdk for ZynqMP (7 Replies)
5. How to simulate the bootloader with flash S25fs256s verilog model for pulpino? (0 Replies)
6. Pulpissimo synthesis error (0 Replies)
7. Lower number of cores on HERO (3 Replies)
8. Pulpissimo Synthesis content (3 Replies)
9. How to do post-synthesis simulation of PULPino after generating netlist using DC (2 Replies)
10. [HERO] Userland application debugging (1 Reply)
11. [PULP] Peripheral bus memory map (1 Reply)
12. clock problem when writing sdc file in order to synthesize PULPino (2 Replies)
13. Pulpissimo synthesis (5 Replies)
14. problem when generating boot rom using boot_code.sv (5 Replies)
15. Error When Running hwme example (3 Replies)
16. RI5CY - FPGA Synthesis (0 Replies)
17. Error when building Pulpissimo (2 Replies)
18. [HWPE] Microcode (4 Replies)
19. match problem between Python3 and pip3 (1 Reply)
20. FPGA JTAG-cable and debugger sw (5 Replies)