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Thread / Author			Replies	Views [asc]	Last Post
		Is SYNTHESIS, ASIC_SYNTHESIS Flag needed during Synthesis vignajeth, 05-06-2021, 04:06 PM	1	5,937	06-24-2021, 06:52 AM Last Post: meggiman
		Opentitan on FPGA gtelzur, 06-05-2022, 07:51 AM	2	5,898	06-05-2022, 07:11 PM Last Post: gtelzur
		Question about Pulpissimo memory zorrolee777, 03-06-2021, 02:50 AM	1	5,865	03-06-2021, 06:58 AM Last Post: kgf
		Maximum frequency obtained when synthesizing the RI5CY core multiplier with 28 FD-SOI Olivier, 01-18-2021, 08:57 AM	1	5,815	01-18-2021, 12:57 PM Last Post: kgf
		ri5cy debugger access to memory and breakpoint facility lightning_fingers, 12-27-2018, 09:30 AM	0	5,643	12-27-2018, 09:30 AM Last Post: lightning_fingers
		pwd for the image example Lucas657, 04-07-2021, 08:54 AM	1	5,597	04-07-2021, 09:06 AM Last Post: akurth
		Need Up To Date COIN CBC With Pulp cswor, 03-19-2021, 10:55 PM	1	5,559	03-19-2021, 11:03 PM Last Post: kgf
		Modify input image on MobileNet zumair-19, 10-22-2021, 11:21 AM	1	5,548	10-22-2021, 11:30 AM Last Post: kgf
		pulp optimization problem,not getting expected output. pallavi@76, 06-17-2021, 07:34 AM	1	5,452	06-18-2021, 05:59 AM Last Post: kgf
		The signed/unsigned operation support by the Dotp-Unit of the RI5CY core Olivier, 01-05-2021, 09:42 AM	1	5,447	01-05-2021, 10:53 AM Last Post: kgf
		Printf Statements Breaking Post Simulation vignajeth, 04-20-2021, 05:20 PM	1	5,370	05-04-2021, 04:19 PM Last Post: meggiman
		Tock OS on pulpissimo cyberbemon, 05-31-2021, 02:28 PM	1	5,202	06-01-2021, 11:25 AM Last Post: bluewww
		pulp optimization problem,not getting expected output. pallavi@76, 06-17-2021, 07:33 AM	1	5,084	06-24-2021, 07:05 AM Last Post: meggiman
		Latest Pulpissimo RTL doesn't fit the nexysA7-100T FPGA AhmedZaky, 01-05-2023, 01:40 PM	3	5,059	01-31-2023, 03:53 PM Last Post: kgf
		Is that possible to boot Linux kernel on Pulpissimo with minor changes? ninipa, 08-04-2021, 07:25 AM	1	5,048	08-04-2021, 07:58 AM Last Post: kgf
		Error on Macro 'DMI_JTAG_IDCODE is not defined when built pulp RTL simulation pfm mapletree, 06-21-2019, 05:09 PM	0	5,027	06-21-2019, 05:09 PM Last Post: mapletree
		How to simulate the bootloader with flash S25fs256s verilog model for pulpino? zhouqiang, 05-25-2019, 04:52 AM	0	5,003	05-25-2019, 04:52 AM Last Post: zhouqiang
		PULPino JTAG access MarekPikula, 08-22-2019, 02:15 PM	0	4,964	08-22-2019, 02:15 PM Last Post: MarekPikula
		RI5CY - FPGA Synthesis jaypi, 05-07-2019, 03:20 PM	0	4,935	05-07-2019, 03:20 PM Last Post: jaypi
		Integrating NVDLA with PULPissimo AhmedZaky, 06-13-2019, 04:17 PM	0	4,882	06-13-2019, 04:17 PM Last Post: AhmedZaky
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