Hello again!

The documentation for the ri5cy core, although getting better, is still a little "light" on details for the debugger hardware.

Is there any facility available for accessing memory whilst in debugging mode?
if not, how is it proposed that memory should be accessed when debugging?

what would be the suggested mechanism for implementing a breakpoint mechanism such the executing programme can be run up to a point then the debugger activated?
(I already have a simulation where I can single step the core at a specified simulation clock count, in reality this needs to be at a specified PC).

Thanks in advance

Hello!

I am investigating using the ri5cy core for a commercial application.
Quite some time ago I looked into the ri5cy core via the Embecosm githubu fork:
https://github.com/embecosm/ri5cy

This seems to (now) be a quite old version of the core (32 interrupt inputs, much different csr implementation).

So, I've updated my core payload with the latest ri5cy rtl build.

I now have problems with my prototype interrupt code.
In C I have:


in "main()" {
    set_csr (0x300, 0x00000009);            //enable interrupts?
    write_csr(0x305, my_isr);               // isr address?
   
    // big long delay
    for (int i=0;i<10000;i++) asm("NOP");

}

void __attribute__ ((interrupt())) my_isr (){
    *simresult = (unsigned short int) 0xF111;    // flag result
}

which gives me:
00000300 <my_isr>:
 300: ff010113           addi sp,sp,-16
 304: 00f12423           sw a5,8(sp)
 308: 00e12623           sw a4,12(sp)
 30c: 40002703           lw a4,1024(zero) # 400 <simresult>
 310: 0000f7b7           lui a5,0xf
 314: 11178793           addi a5,a5,273 # f111 <_end+0xece5>
 318: 00f72023           sw a5,0(a4)
 31c: 00c12703           lw a4,12(sp)
 320: 00812783           lw a5,8(sp)
 324: 01010113           addi sp,sp,16
 328: 10000073           eret

The compiler is inserting the correct isr handling code......
But when simulated with the latest ri5cy core I get:
#  - DGB - write 0 into CTRL
#        2465870000 ps: Illegal instruction (core 0) at PC 0x00000328:
#        2469762000 ps: Illegal instruction (core 0) at PC 0x00000328:

I read in the riscv documentation that eret should now probably be an mret.
(At present I am using the embecosm modified toolchain (gcc).)

where can I download the "official" build gcc build tools for the latest ri5cy core (including all of the ri5cy additions like the hardware loop functionality)?

Many thanks in advance

Hello again,

I'm trying to build hero-sdk, specifically hero-gcc-toolchain, for use on a ZCU102 and I'm running into some errors.
The first error is when compiling aeabi_lcsts.c:

Hi,

Can you help me resolve this Busybox version issue?

Hello there,

I currently collect information for my bachelor thesis and want to compare popular RISC-V implementations.
You have a nice graphic 


Does there exist a documentation or has somebody knowledge about how the RISC-V cores match to for example ARM cores.
For example:

RI5CY <-> ARM cortex M0
or
PULPino <-> ARM cortex M0

Greetings from Munich,

Aaron

Edit:
The people over at Si-Five compare their cores here for example https://www.sifive.com/core-designer (scroll to the bottom)

I am getting the error at the time of compilation when iI use -march=RV64.
Even i tried with the rv32 or rv64 also.

Regards
Karthik

I have been trying to migrate PULPino project to Vivado 2018.1 workflow. I have been successfully able to compile hardware-software project to obtain files in sd_image. Setting up and booting the SD Card sets up Programmable Logic (as indicated by blue light). Linux is NOT booting. Please help me identify and fix the problem.

Hello,

I'm building the hero-sdk as per the github instructions but it's failing at the pulp-sdk stage.
Actually I'm trying on 2 systems, Debian 9.2 and Ubuntu 16.04.
Both have the same result and symptoms.
It looks like some files which should be copied from ./pulp-sdk/json-tools to ./pulp-sdk/build/sdk/json-tools are missing. I.E there's no Makefile so make doesn't know what to do.
Anybody on here have an idea what's going wrong?

Hi,

I noticed that Google IPU team reported serveral bugs about RI5CY core in the RISC-V Workshop this MAY. I am wondering whether PULP team has yet fixed them in the Github release.

Hope for your response.

----- Details about the bugs -----
Bugs found in:
○ Multiplier
○ LSU

Bugs reported in page 12 of  Google's Reports on the evaluation of RI5CY
RISC-V Workshop website: RISC-V Workshop in Barcelona Proceedings
RTL Core for RI5CY Github release

I'd like to ask is there any UVM environment created for PULPINO SOC, or even for one of the following cores:
  1- RI5CY
  2- Zero-riscy

Thanks