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Forum: PULP General questions
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How to do post-synthesis simulation of PULPino after generating netlist using DC |
Posted by: zhouqiang - 05-09-2019, 02:19 PM - Forum: PULP General questions
- Replies (2)
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Hello,
We want to tape out PULPino using SMIC 0.13um technology, and now we have finished DC and got netlist of PULPino, we have generated a 32KB SRAM macro ,the ROM macro and their function mode verilog file. Next, we are going to use the netlist, the RAM and ROM to do a post-synthesis simulation of PULPino. Can someone tell me how to perform post-synthesis simulation of PULPino? Especially, how to test the functions of SRAM and ROM to determine if they are working properly?
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[PULP] Peripheral bus memory map |
Posted by: lukamac - 05-09-2019, 11:05 AM - Forum: PULP General questions
- Replies (1)
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Hello,
I have been working on adding a HWPE to the bigpulp cluster. For start I added the HWPE MAC example into the bigpulp and synthesis passes.
Now, I would like to write an application in HERO-SDK that uses the MAC engine but I could not find the memory map for peripheral bus.
Is there a file in bigpulp which defines offsets of connected peripherals to the peripheral bus or is there any documentation about it?
To be more specific, I would like to know the base address of the HWPE and where it is defined in bigpulp.
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clock problem when writing sdc file in order to synthesize PULPino |
Posted by: zhouqiang - 05-08-2019, 12:53 PM - Forum: PULP General questions
- Replies (2)
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Clock problem when writing sdc file in order to synthesize PULPino
I am now trying to write a constraint file (sdc file) to synthesize PULPino (using DC), but I don't know much about PULPino's RTL design, so it is a challenging task for me,my question is:
1. According to the .xdc file in vivado, I infer that PULPino has three asynchronous clocks clk, spi_clk_i, tck_i. What is the frequency relationship between them?
2. In DC, I use the command get_nets/ports *clk*, I also got a spi_master_clk_o, which looks like an output port. What is it used for? Do I need to constrain it?
3. In the ASIC design, I want to set the frequency of the main clock clk to 100MHz. So, how should I set the frequency for the other two clocks?
4. In addition, I also want to constrain the generated clock. Is there a generated clock in PULPino? How should I find out all the generated clocks and the corresponding source clock?
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Pulpissimo L2 memory access via JTAG |
Posted by: skor - 05-08-2019, 07:41 AM - Forum: PULP General questions
- Replies (8)
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Hello,
I am trying to write and read L2 memory via JTAG . According to datasheet memory map it should be in 0x1c000000...0x1c080000. and in soc_bus_defines there is definition
// MASTER PORT TO L2
`define SOC_L2_START_ADDR 32'h1C00_0000
`define SOC_L2_END_ADDR 32'h1FFF_FFFF
However the above parameters are not used anywhere and I can not succesfully write and read to that area. I get always zeros from any memory address that i have tried.
So where is the memory located actually ?
I went through the related RTL codes and found local parameter TCDM_START_ADDRESS, which is set to diffrent memory area, and it looked that might be the used area but still the memory access is not working.
As background:
I have succesfylly read and written quite a many peripheral resister, SOC control registers etc, so the JTAG link as such works.
I have implemented Pulpissomo on KIntex FPGA on Genesys board. The xilinx memories seem to be in shape.
Regards, skor
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Pulpissimo synthesis |
Posted by: MikkeN - 05-07-2019, 04:19 PM - Forum: PULP General questions
- Replies (5)
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Hi,
are you having some scripts or tools to help making correct code parsing for synthesis?
I have made my own list, but don't know which files should be included. For example there is axi_slice_dc_master_wrap.sv under axi and pulp_soc.
Is there some automation hidden for src_files.yml files under IPs and RTL?
Currently when running synthesis with dc_shell, it gives errors from some of IPs. I assume that those are not needed in Pulpino implementation.
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error when using DC to synthesis pulpino |
Posted by: zhouqiang - 05-05-2019, 03:21 PM - Forum: PULP General questions
- Replies (2)
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I tried to use DC to synthesize pulpino, but the following error occurred:
Error: ../input_data/control_tp.sv:34: Unable to open file `fpu_defs_div_sqrt_tp.pvk': in search_path {/home/ichip/Desktop/PULPino_scripts/DC/tmp . /eda/synopsys/syn_vH-2013.03/libraries/ Syn /eda/synopsys/syn_vH-2013.03/minpower/syn /eda/synopsys/syn_vH-2013.03/dw/syn_ver /eda/synopsys/syn_vH-2013.03/dw/sim_ver}. (VER-292)
I opened control_tp.sv and found line 34 is:
Import fpu_defs_div_sqrt_tp::*;
It seems that this sentence caused DC to make a mistake. Can someone help me to see what this sentence means? How should I solve this error? In addition, when using DC to synthesis pulpino, what should be noted?
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[HWPE] Microcode |
Posted by: lukamac - 05-04-2019, 01:23 PM - Forum: PULP General questions
- Replies (4)
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Hello,
I found a word document describing the HWPE Interface Specification, Rev 1.2, written in January 2018. by Francesco Conti.
I would like to use the microcode capabilities of the HWPE so I read there, since in the online Interface specification I couldn't find anything about it.
In this document, there was a mention of a Pythong script ucode_compile.py that should be able to compile some high-level code for the microcode processor.
Unfortunately, I could not find it so I have a few questions now.
Is the Microcode processor in the HWPE usable?
Is there somewhere such a "compiler" for microcode?
If it should be hardcoded, is there a specification of the instruction encoding? I found very little information about this in the document.
Thank you in advance!
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