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Pulpissimo bitstream gene...
Forum: PULP General questions
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Yesterday, 06:41 AM
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Help to run Hello Example
Forum: PULP General questions
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Yesterday, 06:31 AM
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Compiling and running app...
Forum: PULP General questions
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Yesterday, 06:13 AM
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How do I get the files ne...
Forum: PULP General questions
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02-29-2024, 12:36 AM
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Understanding the TCDM in...
Forum: PULP General questions
Last Post: zealshah29
02-13-2024, 10:34 AM
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Error while updating IPs
Forum: PULP General questions
Last Post: zealshah29
02-08-2024, 06:03 AM
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Snitch cluster: make bin/...
Forum: PULP General questions
Last Post: ashuthosh
02-07-2024, 07:38 AM
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Synthesizable Version of ...
Forum: PULP General questions
Last Post: cykoenig
01-16-2024, 10:52 AM
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RISC V proyect research
Forum: PULP General questions
Last Post: kgf
12-29-2023, 01:09 PM
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PULPino Boot ROM Address ...
Forum: PULP General questions
Last Post: kgf
12-29-2023, 12:54 PM
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pulp-soc-defines.sv |
Posted by: MikkeN - 04-18-2019, 08:17 AM - Forum: PULP General questions
- No Replies
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Hi,
there is no too much documentation in pulp-soc-defines.sv file. So could you clarify next statement:
// PE selection (only for non-FPGA - otherwise selected via PULP_CORE env variable)
// -> define RISCV for RISC-V processor
//`define RISCV
//PARAMETRES
`define NB_CLUSTERS 1
`define NB_CORES 8
`define NB_DMAS 4
`define NB_MPERIPHS 1
`define NB_SPERIPHS 8
-> Does this mean that in normal configuration there is 8 cores if?
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Errors encountered when compiling the toolchain |
Posted by: zhouqiang - 04-17-2019, 02:07 PM - Forum: PULP General questions
- Replies (2)
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hello,
When I compiled the toolchain according to the steps in https://github.com/pulp-platform/pulp-ri...-toolchain, I encountered the following error:
/tmp/ccIifWI0.s: Assembler messages:
/tmp/ccIifWI0.s:4963: Error: unrecognized opcode `lwu a1,.LANCHOR0 2'
/tmp/ccIifWI0.s:5179: Error: unrecognized opcode `lwu a5,.LANCHOR0'
/tmp/ccIifWI0.s:5258: Error: unrecognized opcode `lwu a4,.LANCHOR0 2'
/tmp/ccIifWI0.s:5905: Error: unrecognized opcode `lwu a2,.LANCHOR0 2'
/tmp/ccIifWI0.s:5997: Error: unrecognized opcode `lwu a3,.LANCHOR0 2'
/home/lee/Downloads/pulp-riscv-gnu-toolchain/riscv-gcc/libgcc/static-object.mk:17: recipe for target 'unwind-dw2.o' failed
Make[2]: *** [unwind-dw2.o] Error 1
Make[2]: Leaving directory '/home/lee/Downloads/pulp-riscv-gnu-toolchain/build-gcc-linux-stage1/riscv32-unknown-linux-gnu/libgcc'
Makefile:11207: recipe for target 'all-target-libgcc' failed
Make[1]: *** [all-target-libgcc] Error 2
Make[1]: Leaving directory '/home/lee/Downloads/pulp-riscv-gnu-toolchain/build-gcc-linux-stage1'
Makefile:150: recipe for target 'stamps/build-gcc-linux-stage1' failed
Make: *** [stamps/build-gcc-linux-stage1] Error 2
Since I am going to install the cross complier to /home/lee/Downloads/complier, so I run the commands below :
1./configure --prefix=/home/lee/Downloads/complier --with-arch=rv32g --with-abi=ilp32d
2.make linux
Is the install path chosen like this? Why is there such an error? How can I resolve these errors?
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Error When Running hwme example |
Posted by: AhmedZaky - 04-16-2019, 04:55 AM - Forum: PULP General questions
- Replies (3)
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Hi,
I am currently trying to use PULPissimo and the hello example runs fine, however when I try to run hwme example I got this error:
" [/sys/board/chip/soc/fc/warning ] Invalid access (offset: 0x1a10c004, size: 0x4, is_write: 0)"
Also Modelsim gui doesn't open when I use this command for hello example " make clean all run gui=1 "
Can anyone passed this help in figuring out what's the problem ?
Thanks in advance.
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RISC-V GNU Compiler Toolchain: Build Error |
Posted by: AhmedZaky - 04-15-2019, 09:24 AM - Forum: PULP General questions
- Replies (4)
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Hi,
I am trying to build the "RISC-V GNU Compiler Toolchain" as a step for building the SDK for PULPissimio platform. When I try to execute the following command :
Code: ./configure --prefix=/opt/riscv
make linux
I got this error:
/tmp/cczwQOyT.s: Assembler messages:
/tmp/cczwQOyT.s:5044: Error: unrecognized opcode `ldu a1,.LANCHOR0+2'
/tmp/cczwQOyT.s:5279: Error: unrecognized opcode `ldu a5,.LANCHOR0'
/tmp/cczwQOyT.s:5357: Error: unrecognized opcode `ldu a4,.LANCHOR0+2'
/tmp/cczwQOyT.s:6002: Error: unrecognized opcode `ldu a2,.LANCHOR0+2'
/tmp/cczwQOyT.s:6094: Error: unrecognized opcode `ldu a3,.LANCHOR0+2'
/home/ahmed/pulp-riscv-gnu-toolchain/riscv-gcc/libgcc/static-object.mk:17: recipe for target 'unwind-dw2.o' failed
make[2]: *** [unwind-dw2.o] Error 1
make[2]: Leaving directory '/home/ahmed/pulp-riscv-gnu-toolchain/build-gcc-linux-stage1/riscv64-unknown-linux-gnu/libgcc'
Makefile:11207: recipe for target 'all-target-libgcc' failed
make[1]: *** [all-target-libgcc] Error 2
make[1]: Leaving directory '/home/ahmed/pulp-riscv-gnu-toolchain/build-gcc-linux-stage1'
Makefile:150: recipe for target 'stamps/build-gcc-linux-stage1' failed
make: *** [stamps/build-gcc-linux-stage1] Error 2
I searched for a similar error but I found no solution for this. Hopefully someone will be able to help me solving this error as I am new linux user.
Thanks in advance !
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What do I need to do before a taping out of PULPino? |
Posted by: zhouqiang - 04-14-2019, 12:35 PM - Forum: PULP General questions
- Replies (5)
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Hello,
I am a student a complete novice in SOC design. Our tutor wants to implement a RISCV chip design on the extra area of the MPW. If I want to tape out PULPino, what should I verify first?
As far as I know, PULPino is a very mature project, and it has been taped out in different processes, so my current idea is:
1. Perform a Verilog simulation test. The assembly code of the instruction is compiled into a binary file to be read by Verilog's readmemh function, and then all instructions are tested one by one until all instructions pass the test. This part of the test should only involve the operation of the instruction set in the RISCY core.
2. Perform FPGA prototype verification on PULPino SOC. The purpose of this process is to download the SOC's Verilog code to the FPGA and then run the program on the FPGA. It may be necessary to use GDB and OpenOCD for debugging.
Is my idea correct? Does the PULPino project support the above two verifications? Can you give me some advice? And what should be noted in the tool chain, environment, SDK, etc.?
Thanks
zhouqiang
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Pulpissimo on FPGA |
Posted by: skor - 04-09-2019, 12:28 PM - Forum: PULP General questions
- Replies (1)
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Hello,
I have been trying to Synthesize and implement Pulpissimo on Xilinx FPGA using Vivado . There are problems in the syntesized design although elaborated design seems to be Okay. Have you synthesised Pulpissimo using VIvado and if yes then did you have to do changes to the RTL?
My synthesis basically is completed succesfully, but when I look at the synthesised schematics I can see that for example zynq_clk_i is not connected anywhere, although it should go to ref_clk_i in soc_domain.
Regards, Sirpa
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Coremark for benchmarking 8 core PULP |
Posted by: Athena - 03-28-2019, 01:39 PM - Forum: PULP General questions
- Replies (2)
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Hello,
I want to benchmark the performance of the 8 core multicore platform PULP. The current coremark example in pulp-rt-examples needs to be modified to be able to run it on PULP such that it uses the 8 cores of the cluster. Can a guideline be provided to modify the Coremark benchmark for the PULP platform.
Regards,
Athena
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FPGA JTAG-cable and debugger sw |
Posted by: Akim - 03-28-2019, 11:45 AM - Forum: PULP General questions
- Replies (5)
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Hello,
We have bought couple of Genesys2 FPGA boards. We are going to use the Pulpissimo for that.
We would like to flash the test software to it and also if possible use some debugging software via JTAG.
Do you have any suggestion to use as JTAG-cable or debugging software, that you are going to support?
Do I need to use Genesys2 PMOD connectors to connect JTAG-cable or do you have any solid solutions for that?
If understood correctly debugging software is going to need OpenOCD support and that is coming Q2/2019 for Pulpissimo. Right?
Br,
Akim
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