Hey, 


I am facing an issue with running the hwme example on pulpissimo both in bare metal code and FPGA. I had an earlier versions of RTL, SDK and I managed to run the example successfully on the platform. Now the code never reach the end of the code and print the number of errors. 

Are you aware with such a problem, what could be the source of this error ? I thinks there is a problem in plp_hwme_enable() function, it never passes this line. 

Thanks for your support !

Hi,
I am trying to build the pulp RTL simulaltion platform following the instructions provided on the github page:
https://github.com/pulp-platform/pulp.

At the steps:

Hey All, 

I am trying to integrate NVDLA accelerator into PULPissimo platform through AXI4 interface. Has anyone done it before ? What's the limitations in terms of both hardware and software integration ? 

Thanks !

Hi,

we are using the ri5cy core, pulpinov1 branch, and wanted to understand which spike (isa simulator) repository should be taken.

i have found this:
https://github.com/pulp-platform/riscv-isa-sim
1. is there a specific branch matching the pulpinov1 design version
2. does it have any specific ri5cy compliance, special flags or any other?
3. am i supposed to take any patch to make it match ri5scy, as the toolchain?

for the toolchain, we are taking this :
https://github.com/pulp-platform/ri5cy_gnu_toolchain
which i understand patches the original pulp platform toolchain to match the ri5cy.

would appreciate any help on this topic.

thanks,
Itay K.

Hi,

In Pulpissimo in l2_ram_multi_bank.sv there is hooks for xilinx memories:
`ifdef PULP_FPGA_EMUL

      logic [NB_BANKS-1:0][7:0]   wea;

      genvar                      i,j;
      generate
         for(i=0; i<NB_BANKS; i++)
         begin : CUTS
            for(j=0; j<8; j++)
            assign wea[i][j] = ~mem_slave[i].csn & ~mem_slave[i].wen & mem_slave[i].be[j];

            xilinx_l2_mem_8192x64 l2_mem_i (
               .clka  ( clk_i                                ),
               .rsta  ( ~rst_ni                              ),
               .ena   ( ~mem_slave[i].csn                    ),
               .wea   ( wea[i]                               ),
               .addra ( mem_slave[i].add[MEM_ADDR_WIDTH-1:0] ),
               .dina  ( mem_slave[i].wdata                   ),
               .douta ( mem_slave[i].rdata                   )
            );
         end
      endgenerate

Have you tested this is working?

Regards, skor

Hi, we are developing a RISC-V project which need to add some ISRs for peripheral hardware, is there any tutorial or example to reference??

thanks!!

Hi!

I would like to use eu_evt_maskWaitAndClr() HAL function to put the RISC-V core to sleep until my HWPE signals an event (job done). I am using HERO-SDK.
I tried including eu_v3.h header in my code (between #pragma omp declare target and #pragma omp end declare target), but compiler gives me fatal error: eu_v3.h: No such file or directory. Is it even posible to use headers from pulp-sdk inside hero-sdk project?

Best regards,
Tomislav

Hi,
  I want to try to simluate the bootloader with flash S25fs256s,  so that I can simluate with the  flash. I have found the verilog model of S25fs256s according to https://github.com/pulp-platform/pulpiss.../spi_flash, and I have instantiated the generic pad for each signal coming from my SPI model according to https://github.com/pulp-platform/pulpino/issues/16, and in order to test boot_code, I changed MEMLOAD on https://github.com/pulp-platform/pulpino/blob/master/vsim/tcl_files/run.tcl, from PRELOAD to STANDALONE.  I instantiated the flash module in the pulpion_top file, but when I run "make testSPIMASTER.vsim" or "make helloworld.vsim" ,  but still encounter the error  "RX string: ERROR: Spansion SPI flash not found” ，can someone tell me how to deal with the error? How can make it to find the Spanison SPI flash ?

Hi,

I got following error when synthesising (dc_shell L2016-03) Pulpissimo:


Information: Building the design 'pulp_soc' instantiated from design 'soc_domain_0_1_32_64_32_6_4_6_8_4_8_8' with
        the parameters "CORE_TYPE=0,USE_FPU=1,AXI_ADDR_WIDTH=32,AXI_DATA_IN_WIDTH=64,AXI_DATA_OUT_WIDTH=32,AXI_ID_IN_WIDTH=6,AXI_ID_OUT_WIDTH=4,AXI_USER_WIDTH=6,EVNT_WIDTH=8,BUFFER_WIDTH=8". (HDL-193)
Error:  ../pulpissimo/ips/pulp_soc/rtl/pulp_soc/pulp_soc.sv:269: Syntax error at or near token 'FC_Core_MHARTID': arrays do not have named members. (VER-294)
*** Presto compilation terminated with 2 errors. ***

MikkeN